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A Preprocessing High-Speed Memory System
September 1970 (vol. 19 no. 9)
pp. 793-802
| ASCII Text | x | ||
| D.J. Kuck, "A Preprocessing High-Speed Memory System," IEEE Transactions on Computers, vol. 19, no. 9, pp. 793-802, September, 1970. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1970.223042, author = {D.J. Kuck}, title = {A Preprocessing High-Speed Memory System}, journal ={IEEE Transactions on Computers}, volume = {19}, number = {9}, issn = {0018-9340}, year = {1970}, pages = {793-802}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1970.223042}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Preprocessing High-Speed Memory System IS - 9 SN - 0018-9340 SP793 EP802 EPD - 793-802 A1 - D.J. Kuck, PY - 1970 KW - Array processing KW - data prefetching KW - interleaved memories KW - parallel processing KW - pipeline processing KW - sparse matrix operations KW - table lookup. VL - 19 JA - IEEE Transactions on Computers ER - | |||
The fastest parallel and pipeline computers presently being designed use interleaved memory systems with more than 16 individual memory units. A common difficulty in these machines is the alignment of data before it is arithmetically processed. Usually the arithmetic unit is used to preprocess the data. This may increase the computation time by a factor of two or more. This paper proposes a programmed memory preprocessing system which aligns the data before it is passed to the arithmetic processor.
Index Terms:
Array processing, data prefetching, interleaved memories, parallel processing, pipeline processing, sparse matrix operations, table lookup.
Citation:
D.J. Kuck, "A Preprocessing High-Speed Memory System," IEEE Transactions on Computers, vol. 19, no. 9, pp. 793-802, Sept. 1970, doi:10.1109/T-C.1970.223042
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