To meet the challenge created by the advent of large- scale integration, a unique microelectronic arithmetic building element and combinational arithmetic nets, composed of the building elements, have been studied and proposed for arithmetic processor design. A fast division algorithm, particularly suitable for floating- point arithmetic, has also been developed for signed-digit arithmetic. This algorithm is characterized by the need of preprocessing the divisor and then exact generation of quotient digits. This paper describes the implementation of this division algorithm with the arithmetic building element and combinational arithmetic nets. The intention here is to explore the feasibility of applying large-scale integration technology to arithmetic processors.