This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fast Multipliers
February 1970 (vol. 19 no. 2)
pp. 153-157
A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.
Index Terms:
Dadda's multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace's multipliers.
Citation:
A. Habibi, P.A. Wintz, "Fast Multipliers," IEEE Transactions on Computers, vol. 19, no. 2, pp. 153-157, Feb. 1970, doi:10.1109/T-C.1970.222881
Usage of this product signifies your acceptance of the Terms of Use.