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Issue No.02 - February (1970 vol.19)
pp: 153-157
ABSTRACT
A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.
INDEX TERMS
Dadda's multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace's multipliers.
CITATION
A. Habibi, P.A. Wintz, "Fast Multipliers", IEEE Transactions on Computers, vol.19, no. 2, pp. 153-157, February 1970, doi:10.1109/T-C.1970.222881
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