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February 1970 (vol. 19 no. 2)
pp. 116-124
In this paper we concern ourselves with the problem of obtaining high sequence rate sequential machines, machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devi
Index Terms:
Badly timed devices, clocked logic, completeness of synchronous logic, high-speed logic, maximum rate construction.
Citation:
H.H. Loomis, "A Scheme for Synchronizing High-Speed Logic Part II," IEEE Transactions on Computers, vol. 19, no. 2, pp. 116-124, Feb. 1970, doi:10.1109/T-C.1970.222876
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