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Mathematical ``Lower Bounds'' and the Logic Circuit Designer
January 1970 (vol. 19 no. 1)
pp. 80-81
A. S. Farber, IBM Watson Research Ctr., Yorktown Heights, N. Y.; Responsive Data Processing Corporation, Mt, Kisco, N. Y.
E. S. Schlig, IBM Watson Research Ctr., Yorktown Heights, N. Y.
The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder.
Citation:
A. S. Farber, E. S. Schlig, "Mathematical ``Lower Bounds'' and the Logic Circuit Designer," IEEE Transactions on Computers, vol. 19, no. 1, pp. 80-81, Jan. 1970, doi:10.1109/TC.1970.5008905
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