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Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II
January 1970 (vol. 19 no. 1)
pp. 66-73
H. Allen Curtis, International Radiant Corp., Williamsburg, Va.
This paper is Part II of a two-part study of systematic procedures for realizing synchronous sequential machines using flip-flop memory. In this study the methods of Dolotta and McCluskey, and Weiner and Smith are generalized so that they can be used to obtain directly good realizations of machines using flip-flop memory. In Part I the generalizations were simple, straightforward, and required a minimal amount of changes to the basic methods. For machines using trigger flip-flop memory or a combination of trigger and set-reset, or trigger and J-K flip-flops, these generalizations usually yield significantly better realizations than those obtained from the use of the ungeneralized versions of these methods along with methods for transforming the resulting next-state functions into flip-flop input functions. Minimization of changes of these methods was achieved at the expense of imposing the restriction that the inputs to each of the set-reset and J-K flip-flop types be complementary. In the present paper further generalizations for obtaining even better realizations using trigger, set-reset, and J-K flip-flops are developed by dropping the aforementioned restriction.
Citation:
H. Allen Curtis, "Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II," IEEE Transactions on Computers, vol. 19, no. 1, pp. 66-73, Jan. 1970, doi:10.1109/TC.1970.5008901
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