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An Error-Detecting Binary Adder: A Hardware-Shared Implementation
January 1970 (vol. 19 no. 1)
pp. 34-38
Terry G. Gaddess, Coordinated Science Laboratory, University of Illinois, Urbana, Ill. 61801.; Texas Instruments, Inc., Dallas, Tex. 75222.
A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry.
Citation:
Terry G. Gaddess, "An Error-Detecting Binary Adder: A Hardware-Shared Implementation," IEEE Transactions on Computers, vol. 19, no. 1, pp. 34-38, Jan. 1970, doi:10.1109/TC.1970.5008897
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