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An Algorithm for NAND Decomposition Under Network Constraints
December 1969 (vol. 18 no. 12)
pp. 1098-1109
A branch-and-bound algorithm is presented for the synthesis of multioutput, multilevel, cycle-free NAND networks to realize an arbitrary given set of partially or completely specified combinational switching functions. In a programmed version of the algorithm, fan-in, fan-out, and level constraints may be specified. Cost may be specified as a nonnegative integer linear combination of gates and gate inputs. Further constraints and cost criteria are compatible with the algorithm. A first solution is constructed by a sequence of local decisions, and backtracking is executed to find improved solutions and to prove the optimality of the final solution.
Index Terms:
Branch-and-bound algorithm, circuit constraints, combinational logic synthesis, decomposition, logic design automation, NAND synthesis.
E.S. Davidson, "An Algorithm for NAND Decomposition Under Network Constraints," IEEE Transactions on Computers, vol. 18, no. 12, pp. 1098-1109, Dec. 1969, doi:10.1109/T-C.1969.222593
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