|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
Logical Design Using Shift Registers
October 1969 (vol. 18 no. 10)
pp. 958-960
| ASCII Text | x | ||
| W.A. Davis, "Logical Design Using Shift Registers," IEEE Transactions on Computers, vol. 18, no. 10, pp. 958-960, October, 1969. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1969.222554, author = {W.A. Davis}, title = {Logical Design Using Shift Registers}, journal ={IEEE Transactions on Computers}, volume = {18}, number = {10}, issn = {0018-9340}, year = {1969}, pages = {958-960}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1969.222554}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Logical Design Using Shift Registers IS - 10 SN - 0018-9340 SP958 EP960 EPD - 958-960 A1 - W.A. Davis, PY - 1969 KW - Logical design KW - sequential machine KW - shift register KW - state assignment. VL - 18 JA - IEEE Transactions on Computers ER - | |||
This correspondence presents a logical design procedure for feedback shift registers, which permits the gating of a common clock signal.
Index Terms:
Logical design, sequential machine, shift register, state assignment.
Citation:
W.A. Davis, "Logical Design Using Shift Registers," IEEE Transactions on Computers, vol. 18, no. 10, pp. 958-960, Oct. 1969, doi:10.1109/T-C.1969.222554
Usage of this product signifies your acceptance of the Terms of Use.