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Worst-Case Analysis of a Resistor Memory Matrix
October 1969 (vol. 18 no. 10)
pp. 940-942
| ASCII Text | x | ||
| W.T. Lynch, "Worst-Case Analysis of a Resistor Memory Matrix," IEEE Transactions on Computers, vol. 18, no. 10, pp. 940-942, October, 1969. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1969.222549, author = {W.T. Lynch}, title = {Worst-Case Analysis of a Resistor Memory Matrix}, journal ={IEEE Transactions on Computers}, volume = {18}, number = {10}, issn = {0018-9340}, year = {1969}, pages = {940-942}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1969.222549}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Worst-Case Analysis of a Resistor Memory Matrix IS - 10 SN - 0018-9340 SP940 EP942 EPD - 940-942 A1 - W.T. Lynch, PY - 1969 KW - Fixed memories KW - READ-only memories KW - resistor matrices KW - switchable resistor matrices KW - worst-case analysis of resistor matrices. VL - 18 JA - IEEE Transactions on Computers ER - | |||
The worst-case output voltage ratio Vs (1)min /Vs (0)max is derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.
Index Terms:
Fixed memories, READ-only memories, resistor matrices, switchable resistor matrices, worst-case analysis of resistor matrices.
Citation:
W.T. Lynch, "Worst-Case Analysis of a Resistor Memory Matrix," IEEE Transactions on Computers, vol. 18, no. 10, pp. 940-942, Oct. 1969, doi:10.1109/T-C.1969.222549
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