This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Worst-Case Analysis of a Resistor Memory Matrix
October 1969 (vol. 18 no. 10)
pp. 940-942
W.T. Lynch, IEEE
The worst-case output voltage ratio Vs(1)min/Vs(0)maxis derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.
Index Terms:
Fixed memories, READ-only memories, resistor matrices, switchable resistor matrices, worst-case analysis of resistor matrices.
Citation:
W.T. Lynch, "Worst-Case Analysis of a Resistor Memory Matrix," IEEE Transactions on Computers, vol. 18, no. 10, pp. 940-942, Oct. 1969, doi:10.1109/T-C.1969.222549
Usage of this product signifies your acceptance of the Terms of Use.