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Issue No.10 - October (1969 vol.18)
pp: 890-894
ABSTRACT
In this paper a practical approach to generate fault detection tests for four-phase MOS LSI circuits is discussed. Emphasis is given to a computer aid on the generation of both primary output and primary input test sequences. A technique to preset the circuit to predictable logic levels is presented.
INDEX TERMS
Computer aid, four-phase, LSI, MOS, test generation.
CITATION
null Yao Tung Yen, "Computer-Aided Test Generation for Four-Phase MOS LSI Circuits", IEEE Transactions on Computers, vol.18, no. 10, pp. 890-894, October 1969, doi:10.1109/T-C.1969.222543
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