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The ILLIAC IV Processing Element
September 1969 (vol. 18 no. 9)
pp. 800-816
| ASCII Text | x | ||
| R.L. Davis, "The ILLIAC IV Processing Element," IEEE Transactions on Computers, vol. 18, no. 9, pp. 800-816, September, 1969. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1969.222777, author = {R.L. Davis}, title = {The ILLIAC IV Processing Element}, journal ={IEEE Transactions on Computers}, volume = {18}, number = {9}, issn = {0018-9340}, year = {1969}, pages = {800-816}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1969.222777}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - The ILLIAC IV Processing Element IS - 9 SN - 0018-9340 SP800 EP816 EPD - 800-816 A1 - R.L. Davis, PY - 1969 KW - Computer arithmetic KW - ILLIAC IV KW - medium-scale integration KW - parallel processing. VL - 18 JA - IEEE Transactions on Computers ER - | |||
This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc.
Index Terms:
Computer arithmetic, ILLIAC IV, medium-scale integration, parallel processing.
Citation:
R.L. Davis, "The ILLIAC IV Processing Element," IEEE Transactions on Computers, vol. 18, no. 9, pp. 800-816, Sept. 1969, doi:10.1109/T-C.1969.222777
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