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A High-Speed Carry Circuit for Binary Adders
August 1969 (vol. 18 no. 8)
pp. 728-732
A high-speed carry circuit for binary parallel adders is described. The circuit consists of emitter followers connected in series to form a transmission path for carry signals obtained from the individual bits of the adder.
Index Terms:
Binary parallel adders, computer simulation, logic circuitry, operational results, simple fast carry.
Citation:
C.W. Weller, "A High-Speed Carry Circuit for Binary Adders," IEEE Transactions on Computers, vol. 18, no. 8, pp. 728-732, Aug. 1969, doi:10.1109/T-C.1969.222755
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