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January 1969 (vol. 18 no. 1)
pp. 71-74
With a suitable adder organization it is possible to overlap the adder operation during a binary multiplication and significantly decrease the overall multiplication time. The method is explained and a prototype multiplier described. The new technique provides a very economical method of obtaining a reasonably fast multiplier.
Index Terms:
Concurrent ADD cycles, parallel binary multiplier, propagating adder control signals, synchronous adder.
Citation:
P.M. Fenwick, "Binary Multiplication with Overlapped Addition Cycles," IEEE Transactions on Computers, vol. 18, no. 1, pp. 71-74, Jan. 1969, doi:10.1109/T-C.1969.222527
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