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Issue No.09 - September (1968 vol.17)
pp: 885-886
ABSTRACT
Abstract?A new method of designing and implementing intrinsically failure-tolerant counters with error-correcting state assignments is proposed. Threshold logic elements are used, and state recovery circuitry is united with the flip-flop input logic. A decimal counter built according to this method requires considerably fewer components and has a lower probability of failure at less cost than a diode logic version.
INDEX TERMS
Index Terms?Counter, failure-tolerant design, error-correcting reliability, state assignment, threshold logic.
CITATION
J. Beister, "On the Implementation of Failure-Tolerant Counters", IEEE Transactions on Computers, vol.17, no. 9, pp. 885-886, September 1968, doi:10.1109/TC.1968.229147
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