A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation

Y.T. Yen

doi:10.1109/TC.1968.229140

Publication
1968
Issue No. 9 - September
Abstract - A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation

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A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation

September 1968 (vol. 17 no. 9)

pp. 822-826

	ASCII Text	x
	Y.T. Yen, "A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation," IEEE Transactions on Computers, vol. 17, no. 9, pp. 822-826, September, 1968.

	BibTex	x
	@article{ 10.1109/TC.1968.229140, author = {Y.T. Yen}, title = {A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation}, journal ={IEEE Transactions on Computers}, volume = {17}, number = {9}, issn = {0018-9340}, year = {1968}, pages = {822-826}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1968.229140}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - JOUR JO - IEEE Transactions on Computers TI - A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation IS - 9 SN - 0018-9340 SP822 EP826 EPD - 822-826 A1 - Y.T. Yen, PY - 1968 KW - Index terms?Computer simulation KW - four-phase KW - logic simulation KW - LSI array KW - model KW - MOS circuit. VL - 17 JA - IEEE Transactions on Computers ER -

Y.T. Yen, IEEE

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.1968.229140

Abstract?Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits. In this paper, a mathematical model which characterizes the circuits is presented for logic simulation. It is shown that this model enables us to develop a computer program which can rapidly and efficiently verify and evaluate the logic design of the circuits.

Index Terms:

Index terms?Computer simulation, four-phase, logic simulation,LSI array, model, MOS circuit.

Citation:

Y.T. Yen, "A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation," IEEE Transactions on Computers, vol. 17, no. 9, pp. 822-826, Sept. 1968, doi:10.1109/TC.1968.229140

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