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Issue No.06 - June (1968 vol.17)
pp: 566-578
ABSTRACT
Abstract?In this paper, methods are presented for designing error-correcting capabilities into threshold gate networks so that the logic gates themselves will correct errors of other gates in the network . In all but one of these methods, a given realization is modified by the addition of redundant gates to obtain an error-correcting network . Realizations are obtained by the first three methods which require that an error of any given number of gates be corrected by the gates immediately following those which are in error. This is the multiplexed realization. In the remaining methods, this requirement is replaced by the requirement that a given number of errors be corrected by some gates in the network. Errors of the output gate are not corrected. The last section discusses a method for obtaining an error-correcting network directly from the Boolean function to be realized.
INDEX TERMS
Index Terms?Combinational logic, error-correcting networks, redundancy, threshold networks.
CITATION
J.D. Bargainer, C.L. Coates, "Minimal Multiplexed Threshold Gate Realizations", IEEE Transactions on Computers, vol.17, no. 6, pp. 566-578, June 1968, doi:10.1109/TC.1968.226922
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