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February 1968 (vol. 17 no. 2)
pp. 182-184
| ASCII Text | x | ||
| C.M. Allen, D.D. Givone, "A Minimization Technique for Multiple-Valued Logic Systems," IEEE Transactions on Computers, vol. 17, no. 2, pp. 182-184, February, 1968. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1968.227407, author = {C.M. Allen and D.D. Givone}, title = {A Minimization Technique for Multiple-Valued Logic Systems}, journal ={IEEE Transactions on Computers}, volume = {17}, number = {2}, issn = {0018-9340}, year = {1968}, pages = {182-184}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1968.227407}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Minimization Technique for Multiple-Valued Logic Systems IS - 2 SN - 0018-9340 SP182 EP184 EPD - 182-184 A1 - C.M. Allen, A1 - D.D. Givone, PY - 1968 KW - Index terms?Combinational circuits KW - iterated consensus KW - minimization KW - multiple-valued logic KW - multiple-valued switching functions KW - switching algebra. VL - 17 JA - IEEE Transactions on Computers ER - | |||
Abstract?An algebra for switching circuits that may have multiple values is introduced. A minimization technique suitable for computer implementation is then presented.
Index Terms:
Index terms?Combinational circuits, iterated consensus, minimization, multiple-valued logic, multiple-valued switching functions, switching algebra.
Citation:
C.M. Allen, D.D. Givone, "A Minimization Technique for Multiple-Valued Logic Systems," IEEE Transactions on Computers, vol. 17, no. 2, pp. 182-184, Feb. 1968, doi:10.1109/TC.1968.227407
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