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As the VLSI technology enters the nanoscale regime, VLSI design is increasingly sensitive to variations on process, voltage and temperature. Layer assignment technology plays a crucial role in industrial VLSI design flow. However, existing layer assignment approaches have largely ignored these variations, which can lead to significant timing violations. To address this issue, a variation-aware layer assignment approach for cost minimization is proposed in this work. The proposed layer assignment approach is a single-stage stochastic program that directly controls the timing yield via a single parameter; and it is solved using Monte Carlo simulations and the Latin Hypercube sampling technique. A hierarchical design is also adopted to enable the optimization process on a multi-core platform. Experiments have been performed on 5000 industrial nets, and the results demonstrate that the proposed approach (1) can significantly improve the timing yield by 64.0% in comparison with the nominal design and (2) can reduce the wire cost by 15.7% in comparison with the worst-case design.
Very large scale integration, Stochastic processes, Nanoscale devices, Programming, Capacitance, Optimization,
Shiyan Hu, "Variation-Aware Layer Assignment With Hierarchical Stochastic Optimization on a Multicore Platform", IEEE Transactions on Emerging Topics in Computing, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/TETC.2014.2316503
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