${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist." /> ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist." /> ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist." /> Reverse Engineering Digital Circuits Using Structural and Functional Analyses
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Issue No.01 - March (2014 vol.2)
pp: 63-80
Pramod Subramanyan , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
Nestan Tsiskaridze , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
Wenchao Li , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA
Adria Gascon , Computer Science Laboratory, SRI International, Menlo Park, CA, USA
Wei Yang Tan , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA
Ashish Tiwari , Computer Science Laboratory, SRI International, Menlo Park, CA, USA
Natarajan Shankar , Computer Science Laboratory, SRI International, Menlo Park, CA, USA
Sanjit A. Seshia , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA
Sharad Malik , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
ABSTRACT
Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist.
INDEX TERMS
Algorithm design and analysis, Logic gates, Reverse engineering, Trojan horses, Inference algorithms, Hardware, Globalization, Integrated circuits,
CITATION
Pramod Subramanyan, Nestan Tsiskaridze, Wenchao Li, Adria Gascon, Wei Yang Tan, Ashish Tiwari, Natarajan Shankar, Sanjit A. Seshia, Sharad Malik, "Reverse Engineering Digital Circuits Using Structural and Functional Analyses", IEEE Transactions on Emerging Topics in Computing, vol.2, no. 1, pp. 63-80, March 2014, doi:10.1109/TETC.2013.2294918
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