CSDL - Proceedings V

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-ix

Foreword (PDF)

pp. x

Organizing Committee (PDF)

pp. xi-xiii

Program Committee (PDF)

pp. xiv

Steering Committee (PDF)

pp. xv

Reviewers (PDF)

pp. xvi-xvii

Acknowledgements (PDF)

pp. xviii

Test Technology Technical Council (TTTC) (PDF)

pp. xix-xxi

Test Technology Educational Program (TTEP) Tutorials (PDF)

pp. xxii-xxiv

Awards (PDF)

pp. xxv-xxvii

Efficient Array Characterization in the UltraSPARC T2 (Abstract)

Thomas Ziaja

P.J. Tan

pp. 3-8

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Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller (Abstract)

pp. 9-14

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Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells (Abstract)

pp. 15-20

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An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects (Abstract)

pp. 21-26

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Small Delay Fault Model for Intra-Gate Resistive Open Defects (Abstract)

pp. 27-32

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Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing (Abstract)

Haluk Konuk

pp. 33-38

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Soft-Error Hardening Designs of Nanoscale CMOS Latches (Abstract)

pp. 41-46

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Exploiting Unused Spare Columns to Improve Memory ECC (Abstract)

Rudrajit Datta

Nur A. Touba

pp. 47-52

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An Adaptive-Rate Error Correction Scheme for NAND Flash Memory (Abstract)

pp. 53-58

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Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric (Abstract)

Zheng Wang

Duncan M.H. Walker

pp. 59-64

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Recursive Path Selection for Delay Fault Testing (Abstract)

Jaeyong Chung

Jacob A. Abraham

pp. 65-70

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A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification (Abstract)

pp. 71-76

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Automated Selection of Signals to Observe for Efficient Silicon Debug (Abstract)

Joon-Sung Yang

Nur A. Touba

pp. 79-84

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A New Post-Silicon Debug Approach Based on Suspect Window (Abstract)

pp. 85-90

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Automated Debug of Speed Path Failures Using Functional Tests (Abstract)

Richard McLaughlin

Srikanth Venkataraman

Carlston Lim

pp. 91-96

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Output Hazard-Free Transition Delay Fault Test Generation (Abstract)

pp. 97-102

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Efficient Scheduling of Path Delay Tests for Latch-Based Circuits (Abstract)

Kun Young Chung

Sandeep K. Gupta

pp. 103-110

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Effective and Efficient Test Pattern Generation for Small Delay Defect (Abstract)

Sandeep Kumar Goel

Narendra Devta-Prasanna

Ritesh P. Turakhia

pp. 111-116

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Panel: Apprentice - VTS Edition: Season 2 (Abstract)

Kee Sup Kim

pp. 119

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DFT and Test Problems from the Trenches (Abstract)

Haluk Konuk

pp. 120

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Multiple-Fault Diagnosis Using Faulty-Region Identification (Abstract)

pp. 123-128

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Predictive Test Technique for Diagnosis of RF CMOS Receivers (Abstract)

S. Bota

M. Roca

pp. 129-133

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Controlling DPPM through Volume Diagnosis (Abstract)

pp. 134-139

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Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions (Abstract)

pp. 140-145

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The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost (Abstract)

pp. 146-151

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A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections (Abstract)

pp. 152-157

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False Path Aware Timing Yield Estimation under Variability (Abstract)

Lin Xie

pp. 161-166

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Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study (Abstract)

pp. 167-172

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Yield and Cost Analysis of a Reliable NoC (Abstract)

Saeed Shamshiri

Kwang-Ting Cheng

pp. 173-178

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Restrict Encoding for Mixed-Mode BIST (Abstract)

Abdul-Wahid Hakmi

Stefan Holst

Hans-Joachim Wunderlich

pp. 179-184

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A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset (Abstract)

Keith A. Jenkins

Lionel Li

pp. 185-188

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Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors (Abstract)

pp. 189-194

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Physically-Aware N-Detect Test Relaxation (Abstract)

Yen-Tzu Lin

Chukwuemeka U. Ezekwe

R. D. Blanton

pp. 197-202

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Automatic Selection of Internal Observation Signals for Design Verification (Abstract)

Tao Lv

Hua-wei Li

Xiao-wei Li

pp. 203-208

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STDF Memory Fail Datalog Standard (Abstract)

pp. 209-214

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Testing for Transistor Aging (Abstract)

Altug Hakan Baba

Subhasish Mitra

pp. 215-220

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Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths (Abstract)

pp. 221-226

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Understanding Power Supply Droop during At-Speed Scan Testing (Abstract)

Pankaj Pant

Joshua Zelman

pp. 227-232

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Haralampos Stratigopoulos

Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest (Abstract)

Yiorgos Makris

pp. 233

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Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations (Abstract)

Bernard Courtois

Chandu Visweswariah

pp. 237

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Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips (Abstract)

Bernard Courtois

Ali Shakouri

pp. 241

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Highly X-Tolerant Selective Compaction of Test Responses (Abstract)

pp. 245-250

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Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure (Abstract)

pp. 251-256

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Maintaining Accuracy of Test Compaction through Adaptive Re-learning (Abstract)

Sounil Biswas

R. D. Blanton

pp. 257-263

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RT-Level Deviation-Based Grading of Functional Test Sequences (Abstract)

Hongxia Fang

Krishnendu Chakrabarty

pp. 264-269

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Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering (Abstract)

Naveen Velamati

Robert Daasch

pp. 270-275

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DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study (Abstract)

P. Rech

pp. 276-281

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On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector (Abstract)

pp. 285-290

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Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC (Abstract)

pp. 291-296

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A Time Domain Method to Measure Oscillator Phase Noise (Abstract)

Kenneth Blakkan

Mani Soma

pp. 297-302

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A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources (Abstract)

Erdem Serkan Erdogan

Sule Ozev

pp. 303-308

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Design-for-Testability for Digital Microfluidic Biochips (Abstract)

Tao Xu

Krishnendu Chakrabarty

pp. 309-314

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Stuck-Open Fault Leakage and Testing in Nanometer Technologies (Abstract)

pp. 315-320

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SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration (Abstract)

Unni Chandran

Dan Zhao

pp. 321-326

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Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA (Abstract)

pp. 327-332

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Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing (Abstract)

Bhanu Kapoor

pp. 333

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Panel: Analog Characterization and Test: The Long Road to Realization (Abstract)

pp. 337

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Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough? (Abstract)

Andrew Piziali

pp. 338

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Author Index (PDF)

pp. 339-341

Roster Page (PDF)

pp. 342