CSDL - Proceedings V

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xi

Foreword (PDF)

pp. xii

Committee Lists (PDF)

pp. xiii-xv

Program Committee (PDF)

pp. xvi

Steering Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xviii-xix

Acknowledgements (PDF)

pp. xx

Test Technology Technical Council (TTTC) (PDF)

pp. xxi-xxiii

Test Technology Educational Program (TTEP) Tutorials (PDF)

pp. xxiv-xxvii

Best Paper Awards (PDF)

pp. xxviii-xxx

Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems (Abstract)

Qingqi Dou

Jacob A. Abraham

pp. 3-8

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Test Enabled Process Tuning for Adaptive Baseband OFDM Processor (Abstract)

Muhammad Mudassar Nisar

Abhijit Chatterjee

pp. 9-16

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Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links (Abstract)

Dongwoo Hong

Kwang-Ting(Tim) Cheng

pp. 17-22

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How Many Test Patterns are Useless? (Abstract)

Fran?ois-Fabien Ferhani

pp. 23-28

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Constructing Augmented Multimode Compactors (Abstract)

Emil Gizdarski

pp. 29-34

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Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation (Abstract)

pp. 35-42

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IP Session 1C: Highways to Zero-Defects: Industrial Approaches (PDF)

pp. 43

Inconsistent Fail due to Limited Tester Timing Accuracy (Abstract)

pp. 47-52

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A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips (Abstract)

pp. 53-58

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Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER) (Abstract)

Zhaoliang Pan

Melvin A. Breuer

pp. 59-66

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Diagnosis of Scan Clock Failures (Abstract)

King Leong Lee

Nadir Z. Basturkmen

Srikanth Venkataraman

pp. 67-72

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An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation (Abstract)

pp. 73-78

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On the Detectability of Scan Chain Internal Faults ? An Industrial Case Study (Abstract)

Fan Yang

Sreejit Chakravarty

Narendra Devta-Prasanna

Sudhakar M Reddy

Irith Pomeranz

pp. 79-84

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IP Session 2C: Device Degradation and Infant Mortality (PDF)

pp. 85

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing (Abstract)

A. Ney

pp. 89-94

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An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories (Abstract)

pp. 95-100

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Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry (Abstract)

Niladri Narayan Mojumder

pp. 101-106

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Special Session 3B: New Topic (PDF)

pp. 107

IP Session 3C: Automatic Test Development for Mixed-Signal/RF Circuits (PDF)

pp. 108

Gate-Oxide Early Life Failure Prediction (Abstract)

pp. 111-118

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Full Open Defects in Nanometric CMOS (Abstract)

Daniel Arum?

Rosa Rodr?guez-Monta?

pp. 119-124

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Signature Rollback - A Technique for Testing Robust Circuits (Abstract)

Uranmandakh Amgalan

Christian Hachmann

Sybille Hellebrand

Hans-Joachim Wunderlich

pp. 125-130

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Bounded Adjacent Fill for Low Capture Power Scan Testing (Abstract)

Anshuman Chandra

Rohit Kapur

pp. 131-138

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Reducing Scan Shift Power at RTL (Abstract)

pp. 139-146

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Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes (Abstract)

Yu-Ze Wu

Mango C.-T. Chao

pp. 147-154

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IP Session 4C: Bridging Pre-Silicon Verification and Post-Silicon Validation and Debug (PDF)

pp. 155

Special Session 5A: Embedded Tutorial - Robust Design: Techniques and Trends (PDF)

pp. 159

Special Session 5B: Apprentice - VTS Edition (PDF)

pp. 160

A Time-Domain Method for Pseudo-Spectral Characterization (Abstract)

Apurva Mishra

Mani Soma

pp. 163-168

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A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays (Abstract)

Chen-Wei Lin

Jiun-Lang Huang

pp. 169-174

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Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise (Abstract)

Rajarajan Senguttuvan

Soumendu Bhattacharya

Abhijit Chatterjee

pp. 175-180

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Automatic Test Pattern Generation for Interconnect Open Defects (Abstract)

pp. 181-186

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On the Relaxation of n-detect Test Sets (Abstract)

Stelios Neophytou

Maria K. Michael

pp. 187-192

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Test-Pattern Ordering for Wafer-Level Test-During-Burn-In (Abstract)

Sudarshan Bahukudumbi

Krishnendu Chakrabarty

pp. 193-198

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IP Session 6C: Post-Silicon Validation: Current Practices and New Challenges for the Testing Community (PDF)

pp. 199

Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors (Abstract)

pp. 203-208

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Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers (Abstract)

Erdem Serkan Erdogan

Sule Ozev

pp. 209-214

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ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends (Abstract)

Vishwanath Natarajan

Rajarajan Senguttuvan

Shreyas Sen

Abhijit Chatterjee

pp. 215-220

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Synthesis for Broadside Testability of Transition Faults (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 221-226

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LS-TDF: Low-Switching Transition Delay Fault Pattern Generation (Abstract)

Jeremy Lee

Mohammad Tehranipoor

pp. 227-232

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Test-Pattern Grading and Pattern Selection for Small-Delay Defects (Abstract)

Mahmut Yilmaz

Krishnendu Chakrabarty

Mohammad Tehranipoor

pp. 233-239

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IP Session 7C: Design for Yield and Manufacturability (PDF)

pp. 240

Dynamic Compaction for High Quality Delay Test (Abstract)

Zheng Wang

D.M.H. Walker

pp. 243-248

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An All-Digital High-Precision Built-In Delay Time Measurement Circuit (Abstract)

pp. 249-254

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Error Sequence Analysis (Abstract)

pp. 255-260

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QBIST: Quantum Built-in Self-Test for any Boolean Circuit (Abstract)

pp. 261-266

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Haralampos-G Stratigopoulos

A Statistical Approach to Characterizing and Testing Functionalized Nanowires (Abstract)

James Dardig

pp. 267-274

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A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies (Abstract)

Masoud Hashempour

Zahra Mashreghian Arani

Fabrizio Lombardi

pp. 275-282

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IP Session 8C: STIL Utilization in Practice (PDF)

pp. 283

Special Session 9A: Hot Topic: Yield Management and DPPM Reduction (Abstract)

pp. 287

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Special Session 9B: Embedded Tutorial: Nanoelectronics - What Next? From Moore?s Law to Feynman?s Vision (PDF)

pp. 288

Special Session 9C: TTTC 2008 Best Doctoral Thesis Contest (PDF)

pp. 289

Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits (Abstract)

pp. 293-298

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Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data (Abstract)

Sounil Biswas

R.D. (Shawn) Blanton

pp. 299-308

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Parallel Loopback Test of Mixed-Signal Circuits (Abstract)

pp. 309-316

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Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 317-322

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A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates (Abstract)

Manoj Kumar Goparaju

Spyros Tragoudas

pp. 323-328

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Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults (Abstract)

pp. 329-335

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IP Session 10C: Testing for Complex Failure Mechanisms and Process Variations of Memories (Abstract)

pp. 336

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Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation (Abstract)

pp. 339-344

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Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture (Abstract)

Joon-Sung Yang

Nur A. Touba

pp. 345-351

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A General Failure Candidate Ranking Framework for Silicon Debug (Abstract)

Ten Lin

pp. 352-358

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Special Session 11B: Embedded Tutorial - A Survey of On-Chip Delay Measurement Techniques for Production Test - From Nano to Picoseconds (PDF)

pp. 359

IP Session 11C: New Emerging Practices for Semiconductor Test (PDF)

pp. 360

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms (Abstract)

Carlos Arthur Lang Lisboa

pp. 363-370

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Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors (Abstract)

pp. 371-376

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Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects (Abstract)

Ying Zhang

Huawei Li

Xiaowei Li

Yu Hu

pp. 377-382

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Multiple Coupling Effects Oriented Path Delay Test Generation (Abstract)

pp. 383-388

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A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions (Abstract)

pp. 389-394

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An Industrial Case Study of Sticky Path-Delay Faults (Abstract)

pp. 395-402

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IP Session 12C: Fault Localization Practices and Challenges (PDF)

pp. 403

Special Session 13A: Panel : Mitigating Reliability, Yield and Power Issues in Nano-CMOS: Design Problem or EDA Problem? (PDF)

pp. 407

Special Session 13B: Hot Topic:??Biomedical Devices - New Test Challenges (PDF)

pp. 408

Special Session 13C: Panel: Is Ubiquitous RF at Odds with Test? (PDF)

pp. 409

Author Index (PDF)

pp. 411-412

Roster Page (PDF)

pp. 414