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26th IEEE VLSI Test Symposium (vts 2008)
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
April 27-May 01
ISBN: 0-7695-3123-7
ASCII Text
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Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy, "Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry," VLSI Test Symposium, IEEE, pp. 101-106, 26th IEEE VLSI Test Symposium (vts 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VTS.2008.26,
author = {Niladri Narayan Mojumder and Saibal Mukhopadhyay and Jae-Joon Kim and Ching-Te Chuang and Kaushik Roy},
title = {Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2008},
issn = {1093-0167},
pages = {101-106},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2008.26},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
SN - 1093-0167
SP101
EP106
A1 - Niladri Narayan Mojumder,
A1 - Saibal Mukhopadhyay,
A1 - Jae-Joon Kim,
A1 - Ching-Te Chuang,
A1 - Kaushik Roy,
PY - 2008
KW - Design
KW - failure
KW - SRAM
KW - variation
KW - yield
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve robustness of SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell directly. Computer simulations based on 45nm PD/SOI technology demonstrate the viability and effectiveness of the scheme in SRAM yield enhancement.
Index Terms:
Design, failure, SRAM, variation, yield
Citation:
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy, "Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry," vts, pp.101-106, 26th IEEE VLSI Test Symposium (vts 2008), 2008
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