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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Table of Contents
Session 12C - IP Session: Making the (Yield) Difference: DFY/DFM
Introduction
Papers
Reviewers (PDF)
pp. xviii
Awards (PDF)
pp. xxvii-xxix
Session 1A: Delay Testing I
Session 1B: High Speed Interconnect Test
Ramyanshu Datta, The University of Texas at Austin
Gary Carpenter, IBM Austin Research Laboratory
Kevin Nowka, IBM Austin Research Laboratory
Jacob A. Abraham, The University of Texas at Austin
pp. 24-29
Cristian Grecu, University of British Columbia, Canada
Partha Pande, Washington State University
Andr? Ivanov, University of British Columbia, Canada
Res Saleh, University of British Columbia, Canada
pp. 30-35
Session 1C - IP Session: Reliability Screening Methods for High-Performance Processors in Advanced Technologies
Session 2A: Heat and Power Issues in Test
Minsik Cho, The University of Texas at Austin
David Z. Pan, The University of Texas at Austin
pp. 52-57
Xiaoqing Wen, Kyushu Institute of Technology, Japan
Seiji Kajihara, Kyushu Institute of Technology, Japan
Kohei Miyase, Japan Science and Technology Agency, Japan
Tatsuya Suzuki, Kyushu Institute of Technology, Japan
Kewal K. Saluja, University of Wisconsin - Madison
Laung-Terng Wang, SynTest Technologies
Khader S. Abdel-Hafez, SynTest Technologies
Kozo Kinoshita, Osaka Gakuin University, Japan
pp. 58-65
Session 2B: Test Quality
Session 2C - IP Session: Scan Compression: Techniques, Tradeoffs and Entitlement
Rubin A. Parekhji, Texas Instruments, Ltd., India
pp. 86-87
Session 3A: IP Protection and Interconnect Testing
Jeremy Lee, University of Maryland Baltimore County
Mohammad Tehranipoor, University of Maryland Baltimore County
Jim Plusquellic, University of Maryland Baltimore County
pp. 94-99
Khadija Stewart, Southern Illinois University
Spyros Tragoudas, Southern Illinois University
pp. 100-107
Session 3B: Flash and Memory Testing
O. Ginez, ATMEL Rousset, France
J.-M. Daga, ATMEL Rousset, France
M. Combe, ATMEL Rousset, France
P. Girard, Universit? de Montpellier, France
C. Landrault, Universit? de Montpellier, France
S. Pravossoudovitch, Universit? de Montpellier, France
A. Virazel, Universit? de Montpellier, France
pp. 108-113
Yu-Ying Hsiao, National Tsing Hua University, Taiwan
Chao-Hsun Chen, National Tsing Hua University, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Taiwan
pp. 114-119
Session 3C - IP Session: Nanometer IC Testing: Perspective from Foundries
Cheng-Wen Wu, National Tsing Hua University
pp. 128-129
Session 4A: Yield Analysis
Tong-Yu Hsieh, National Cheng Kung University, Taiwan
Kuen-Jong Lee, National Cheng Kung University, Taiwan
Melvin A. Breuer, University of Southern California
pp. 130-135
Yoshiyuki Nakamura, Nara Institute of Science and Technology, Japan
Jacob Savir, New Jersey Institute of Technology
Hideo Fujiwara, Nara Institute of Science and Technology, Japan
pp. 142-149
Session 4B - New Topic Session: Emerging Nanoelectronic Devices for High-Speed, Low-Power Applications
Bernard Courtois, TIMA-France
pp. 150-151
Session 4C - IP Session: TRP in Action: Embedded Instrumentation in FPGAs
Ajay Khoche, Agilent Technologies
pp. 152-153
Session 5A: - Special Session: The Future of DFT Sector: Point Tools or Integrated Solutions
Yervant Zorian, Virage Logic
Dennis Wassung, Canaccord Adams
pp. 154-155
Session 5B - Special Session: Elevator Talks
Erik Chmelar, LSI Logic
Edward J. McCluskey, Stanford University
pp. 156-157
Session 5C - Embedded Tutorial: Functional ATPG
Praveen Parvathala, Intel Corporation
pp. 158-159
Session 6A: Test Generation and Test Flows
Vlado Vorisek, Freescale Semiconductor
Bruce Swanson, Mentor Graphics Corporation
Kun-Han Tsai, Mentor Graphics Corporation
Dhiraj Goswami, Mentor Graphics Corporation
pp. 160-165
D. Appello, STMicroelectronics - Agrate Brianza (MI), Italy
V. Tancorre, STMicroelectronics - Agrate Brianza (MI), Italy
P. Bernardi, Politecnico di Torino, Italy
M. Grosso, Politecnico di Torino, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
pp. 166-171
Giuseppe Di Guglielmo, Universita di Verona, Italy
Franco Fummi, Universita di Verona, Italy
Cristina Marconcini, Universita di Verona, Italy
Graziano Pravadelli, Universita di Verona, Italy
pp. 172-179
Session 6B: IDDQ, MEMS, and Wireless Testing
Ashutosh Sharma, Colorado State University
Anura P. Jayasumana, Colorado State University
Yashwant K. Malaiya, Colorado State University
pp. 180-185
Rong Zhang, McGill University, Canada
Zeljko Zilic, McGill University, Canada
Katarzyna Radecka, Concordia University, Canada
pp. 186-191
Session 6C - IP Session: Test Strategies of Leading Edge SoCs
Kazumi Hatayama, Renesas Technology Corp.
pp. 200-201
Session 7A: Designing Robust CMOS and Nanoelectronics
Session 7B: RF Testing
Hsieh-Hung Hsieh, National Taiwan University, Taiwan
Liang-Hung Lu, National Taiwan University, Taiwan
pp. 234-239
Session 7C - IP Sessin: High Test Parallelism, Throughput and Quality at a Low Cost: Which Test Cells and Which Partitioning of Test Resources Can Enable All This?
Davide Appello, STMicroelectronics, Italy
pp. 240-241
Session 8A: Test Size Reductions
Wojciech Rajski, Oregon State University
Janusz Rajski, *Mentor Graphics Corporation
pp. 242-251
Session 8B: Transistor Level Diagnosis
Xinyue Fan, Oxford University, UK
Will Moore, Oxford University
Camelia Hora, Philips Research Labs
Mario Konijnenburg, Philips Research Labs
Guido Gronthoud, Philips Research Labs
pp. 266-271
Session 8C - IP Session: Soft Error Impact on Modern Systems
Michael Nicolaidis, TIMA Labs & iRoC Technologies
pp. 286-287
Session 9A - Panel Session: Real-Time Volume Diagnostics: Requirements and Challenges
Ajay Khoche, Semiconductor Test Solutions, Agilent Technologies
Peter Muhmenthaler, Infineon Technologies
pp. 288-289
Session 9B - Special Sesion: Doctoral Thesis Award
Andreas Veneris, University of Toronto
Yiorgos Makris, Yale University
pp. 290-291
Session 9C - Panel Session: Three Questions to Oracle
Session 10A: Delay Testing II
Huawei Li, Chinese Academy of Sciences, China
Peifu Shen, Beijing Normal University, China
Xiaowei Li, Chinese Academy of Sciences, China
pp. 300-305
Jais Abraham, Texas Instruments, India
Uday Goel, Indian Institute of Technology, India
Arun Kumar, Texas Instruments, India
pp. 306-313
Session 10B: Analog Test
Luis Rol?ndez, TIMA Laboratory, France
Salvador Mir, TIMA Laboratory, France
Ahc?ne Bounceur, TIMA Laboratory, France
Jean-Louis Carbon?ro, STMicroelectronics, France
pp. 314-319
Sai Raghuram Durbha, Southern Illinois University
Amit Laknaur, Southern Illinois University
Haibo Wang, Southern Illinois University
pp. 320-325
T. R. Balen, Universidade Federal do Rio Grande do Sul, Brazil
J.V. Calvano, Instituto de Pesquisas da Marinha do Brasil, Brazil
M. S. Lubaszewski, Universidade Federal do Rio Grande do Sul, Brazil
M. Renovell, Universit? de Montpellier II, France
pp. 326-333
Session 10C - IP Session: System-in-Package Design and Test Practices
Yervant Zorian, Virage Logic
Bruce Kim, University of Alabama
pp. 334-335
Session 11A: Delay Testing III
Zhuo Zhang, University of Iowa
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, Purdue University
Xijiang Lin, Mentor Graphics Corp.
Janusz Rajski, Mentor Graphics Corp.
pp. 343-348
Session 11B: Nanoscale Testing
S.A. Bota,, Universitat de les Illes Balears. Spain
M. Rosales, Universitat de les Illes Balears. Spain
J.L. Rossell?, Universitat de les Illes Balears. Spain
J. Segura, Universitat de les Illes Balears, Spain
pp. 358-363
Reza M.P. Rad, University of Maryland Baltimore County
Mohammad Tehranipoor, University of Maryland Baltimore County
pp. 370-377
Session 11C - IP Session: Impact of Variations on Designs and Test
James Tschanz, Intel Corporation
pp. 378-379
Session 12A: Scan Based Diagnosis
P. Bernardi, Politecnico di Torino, Italy
M. Grosso, Politecnico di Torino, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
pp. 386-391
B. Seshadri, Purdue University
I. Pomeranz, Purdue University
S. Venkataraman, Intel Corporation
M.E. Amyeen, Intel Corporation
S.M. Reddy, University of Iowa
pp. 392-399
Session 12B: Mixed Signal Test
C.-Y. Kuo, National Taiwan University, Taiwan
J.-L. Huang, National Taiwan University, Taiwan
pp. 400-405
Hongjoong Shin, The University of Texas at Austin
Byoungho Kim, The University of Texas at Austin
Jacob A. Abraham, The University of Texas at Austin
pp. 412-419
Session 13A: Embedded Tutorial: Silicon Debug Challenges for Nanometer Designs
Rajesh Galivanche, Intel Corporation
Bob Gottlieb, Intel Corporation
pp. 422-423
Session 13B - Hot Topic Session: Signal Integrity: How Can It be Designed into Multiprocessor Platforms, Systems On-Chip, and Systems in-Package?
Andr? Ivanov, University of British Columbia
pp. 424-425
Session 13C - Panel Session: Changing Role of Test: Is ATE Ready?
Ajay Khoche, Semiconductor Test Solutions, Agilent Technologies
Mike Rodgers, Intel Corporation
Pete O?Neil, Avago Technologies
pp. 426
Author Index
Author Index (PDF)
pp. 427-428
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