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24th IEEE VLSI Test Symposium
Iterative OPDD Based Signal Probability Calculation
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
| ASCII Text | x | ||
| Avijit Dutta, Nur A. Touba, "Iterative OPDD Based Signal Probability Calculation," VLSI Test Symposium, IEEE, pp. 72-77, 24th IEEE VLSI Test Symposium, 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/VTS.2006.43, author = {Avijit Dutta and Nur A. Touba}, title = {Iterative OPDD Based Signal Probability Calculation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {72-77}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.43}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Test Symposium, IEEE TI - Iterative OPDD Based Signal Probability Calculation SN - 0-7695-2514-8 SP72 EP77 A1 - Avijit Dutta, A1 - Nur A. Touba, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.43
This paper presents an improved method to accurately estimate signal probabilities using ordered partial decision diagrams (OPDDs) [Kodavarti 93] for partial representation of the functions at the circuit lines. OPDDs which are limited to a certain maximum number of nodes are built iteratively with different variable orderings to efficiently explore different regions of the function. Signal probability bounds (upper and lower) are computed from the OPDDs. From each OPDD, information is extracted to tighten the signal probability bound and guide the variable ordering for the next OPDD. By restricting the size of each OPDD to a small number of nodes, they can be constructed and processed quickly to obtain a fast and accurate estimate of signal probabilities. Experimental results demonstrate the effectiveness of the approach compared with existing methods.
Citation:
Avijit Dutta, Nur A. Touba, "Iterative OPDD Based Signal Probability Calculation," vts, pp.72-77, 24th IEEE VLSI Test Symposium, 2006
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