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24th IEEE VLSI Test Symposium
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Ruifeng Guo, Intel
Subhasish Mitra, Stanford University
Jinkyu Lee, UT Austin
Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs.
Citation:
Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman, "Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive," vts, pp.66-71, 24th IEEE VLSI Test Symposium, 2006
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