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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
ASCII Text
x 
 
Phil Nigh, "Session Abstract," VLSI Test Symposium, IEEE, pp. 44, 24th IEEE VLSI Test Symposium, 2006.
 
 
BibTex
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@article{ 10.1109/VTS.2006.74,
author = {Phil Nigh},
title = {Session Abstract},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2006},
isbn = {0-7695-2514-8},
pages = {44},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.74},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Session Abstract
SN - 0-7695-2514-8
SP
EP
A1 - Phil Nigh,
PY - 2006
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Phil Nigh, IBM
Achieving excellent reliability at reasonable cost is a daunting challenge for high-performance processors on advanced technologies. Major issues are lack of high/low voltage margin, huge leakage currents (particularly at burn-in/stress voltages and temperatures) and new failure modes. In this session, we will have three presentations from industry experts who are on the front lines working on these issues.
Citation:
Phil Nigh, "Session Abstract," vts, pp.44, 24th IEEE VLSI Test Symposium, 2006
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