loading...
  • V
  • VTS
  • 2005
  • 23rd IEEE VLSI Test Symposium (VTS'05)
Advanced Search 
23rd IEEE VLSI Test Symposium (VTS'05)
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
Table of Contents
Introduction
Reviewers (PDF)
pp. xvi-xvii
Plenary Session
Welcome Address
Keynote Address
Program Introduction
Invited Address
Awards Presentations
1A: Memory BIST
Jen-Chieh Yeh, National Tsing Hua University
Yan-Ting Lai, National Tsing Hua University
Yuan-Yuan Shih, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Chien-Hung Ho, eMemory Technology Inc.
Yen-Tai Lin, eMemory Technology Inc.
pp. 15-20
1B: Delay Testing I
Yi-Shing Chang, Intel Corporation
Sreejit Chakravarty, Intel Corporation
Hiep Hoang, Intel Corporation
Nick Thorpe, Intel Corporation
Khen Wee, Intel Corporation
pp. 29-34
Leonard Lee, University of California at Santa Barbara
Li-C. Wang, University of California at Santa Barbara
Praveen Parvathala, Intel Corporation
T. M. Mak, Intel Corporation
pp. 35-41
Nisar Ahmed, Texas Instruments India
C. P. Ravikumar, Texas Instruments India
Mohammad Tehranipoor, Texas Instruments India
Jim Plusquellic, Texas Instruments India
pp. 42-47
1C: IP Session - Multisite Testing
2A: Memory Testing I
Baosheng Wang, University of British Columbia
Yuejian Wu, Nortel Networks
Josh Yang, University of British Columbia
Andr? Ivanov, University of British Columbia
Yervant Zorian, Virage Logic Corporation
pp. 66-71
2B: High-Speed Testing and Clock Skew Compensation
Darren Aaberge, Freescale Semiconductor, Inc.
Ken Mockler, Freescale Semiconductor, Inc.
Dieu Van Dinh, Freescale Semiconductor, Inc.
Raoul Belleau, Teradyne, Inc.
Tim Donovan, Teradyne, Inc.
Reid Hewlitt, Teradyne, Inc.
pp. 75-84
Hitoshi Iwai, Toshiba Corporation Semiconductor Company
Atsushi Nakayama, Toshiba Corporation Semiconductor Company
Naoko Itoga, Toshiba Corporation Semiconductor Company
Kotaro Omata, Apex Inc.
pp. 85-89
Martin Omaña, University of Bologna
Daniele Rossi, University of Bologna
Cecilia Metra, University of Bologna
pp. 90-95
2C: IP Session - DFT for SoCs in Wireless Applications
Abstract (PDF)
pp. 97-97
3A: Test Data Compression and Self-Test
Abdul Wahid Hakmi, Universit?t Stuttgart
Hans-Joachim Wunderlich, Universit?t Stuttgart
Valentin Gherman, Universit?t Stuttgart
Michael Garbers, Philips Semiconductors GmbH
J? Schl?ffel, Philips Semiconductors GmbH
pp. 101-106
Charles H.-P. Wen, University of California at Santa Barbara
Li-C. Wang, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
Kai Yang, University of California at Santa Barbara
Wei-Ting Liu, Industrial Technology Research Institute
Ji-Jan Chen, Industrial Technology Research Institute
pp. 107-113
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
pp. 114-119
3B: Analog Testing I
Anup P. Jose, Columbia University
Keith A. Jenkins, IBM T.J. Watson Research Center
Scott K. Reynolds, IBM T.J. Watson Research Center
pp. 131-136
3C: IP Session - Soft Errors
4A: Defect-Oriented Testing
Benjamin N Lee, University of Califoria at Santa Barbara
Li-C. Wang, University of Califoria at Santa Barbara
Magdy S. Abadir, Freescale Semiconductor
pp. 153-160
Intaik Park, Stanford University
Ahmad Al-Yamani, Stanford University and LSI Logic Corporation
Edward J. McCluskey, Stanford University
pp. 161-166
4B: IP Session - Adaptive Test
4C: IP Session - High Speed I/O Test
5A: Panel Session - Robust Design from Unreliable Components: Why? When? How?
5B: Emerging Technologies - Reliable and Fault-Tolerant Wireless Sensor Networks
6A: Memory Testing II
Luigi Dilillo, Universit? de Montpellier II / CNRS
Patrick Girard, Universit? de Montpellier II / CNRS
Serge Pravossoudovitch, Universit? de Montpellier II / CNRS
Arnaud Virazel, Universit? de Montpellier II / CNRS
Magali Bastian Hage-Hassan, Infineon Technologies France
pp. 183-188
John C. Koob, University of Alberta
Sue A. Ung, University of Alberta
Ashwin S. Rao, University of Alberta
Daniel A. Leder, University of Alberta
Craig S. Joly, University of Alberta
Kristopher C. Breen, University of Alberta
Tyler Brandon, University of Alberta
Michael Hume, University of Alberta
Bruce F. Cockburn, University of Alberta
Duncan G. Elliott, University of Alberta
pp. 189-197
6B: FPGA & MEMS Testing
Chun-Chieh Wang, National Tsing Hua University
Jing-Jia Liou, National Tsing Hua University
Yen-Lin Peng, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 201-206
N. Dumas, Universite Montpellier II/CNRS
F. Aza?, Universite Montpellier II/CNRS
L. Latorre, Universite Montpellier II/CNRS
P. Nouet, Universite Montpellier II/CNRS
pp. 213-218
6C: IP Session - IP in Wireless Testing
7A: Delay Testing II
Matthias Beck, Infineon Technologies AG
Olivier Barondeau, Infineon Technologies AG
Frank Poehl, Infineon Technologies AG
Xijiang Lin, Mentor Graphics Corporation
Ron Press, Mentor Graphics Corporation
pp. 223-228
Yung-Chieh Lin, University of California at Santa Barbara
Feng Lu, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
pp. 229-234
Jing Wang, Texas A&M University
Xiang Lu, Texas A&M University
Wangqi Qiu, Texas A&M University
Ziding Yue, Texas A&M University
Steve Fancler, Texas A&M University
Weiping Shi, Texas A&M University
D. M. H. Walker, Texas A&M University
pp. 235-240
7B: RF Testing
7C: IP Session: Embedded Memory Test & Repair Drives Higher Yield in Nanometer Technologies
8A: Low-Power Testing
Xiaoqing Wen, Kyushu Institute of Technology
Yoshiyuki Yamashita, Kyushu Institute of Technology
Seiji Kajihara, Kyushu Institute of Technology
Laung-Terng Wang, SynTest Technologies, Inc.
Kewal K. Saluja, University of Wisconsin - Madison
Kozo Kinoshita, Osaka Gakuin University
pp. 265-270
Kirti Joshi, University of Texas at El Paso
Eric MacDonald, University of Texas at El Paso
pp. 271-276
8B: Nanometer and Circuit-Level Effects
Abdulkadir U. Diril, Georgia Institute of Technology
Yuvraj S. Dhillon, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
Adit D. Singh, Auburn University
pp. 298-303
8C: IP Session - Test Resource Partitioning in Action
9A: Embedded Tutorial: Test with Variations - How Much Can Be Solved in the Design Process?
9C: Panel Session - Are DFT and Manufacturing Test Good Boosts for DFM?
10A: Reliability
Shalini Ghosh, University of Texas at Austin
Sugato Basu, University of Texas at Austin
Nur A. Touba, University of Texas at Austin
pp. 315-320
10B: Testing of Bridging Faults and Test Scheduling
Sreejit Chakravarty, Intel Corporation
YiShing Chang, Intel Corporation
Hiep Hoang, Intel Corporation
Sridhar Jayaraman, Intel Corporation
Silvio Picano, Intel Corporation
Cheryl Prunty, Intel Corporation
Eric W Savage, Intel Corporation
Rehan Sheikh, Intel Corporation
Eric N. Tran, Intel Corporation
Khen Wee, Intel Corporation
pp. 337-342
Ilia Polian, Albert-Ludwigs-University
Sandip Kundu, Intel Corp.
Jean-Marc Galliere, LIRMM - UMII
Piet Engelke, Albert-Ludwigs-University
Michel Renovell, LIRMM - UMII
Bernd Becker, Albert-Ludwigs-University
pp. 343-348
Chunsheng Liu, University of Nebraska-Lincoln
Vikram Iyengar, IBM Microelectronics
Jiangfan Shi, University of Nebraska-Lincoln
Erika Cota, Universidade Federal do Rio Grande do Sul
pp. 349-354
10C: IP Session - SoC Test Practices in Japan
11A: Diagnosis
11B: Analog Testing II
Gustavo Pereira, University Federal do Rio Grande do Sul
Antonio Andrade Jr., University Federal do Rio Grande do Sul
Tiago R. Balen, University Federal do Rio Grande do Sul
Marcelo Lubaszewski, Universidad Federal do Rio Grande do Sul and Universidad de Sevilla
Florence Aza?, Universit? de Montpellier II
Michel Renovell, Universit? de Montpellier II
pp. 389-394
11C: IP Session - Delay Fault Testing: Industrial Case Studies
12A: Design-for-Testability
Ahmad Al-Yamani, LSI Logic Corporation
Erik Chmelar, LSI Logic Corporation
Mikhail Grinchuck, LSI Logic Corporation
pp. 405-411
Yu-Ting Lin, University of Texas at Austin
Tony Ambler, University of Texas at Austin
pp. 412-417
12B: I_DDQ Testing and Power Supply Noise Analysis
Ritesh Turakhia, Portland State University
Brady Benware, LSI Logic
Robert Madge, LSI Logic
Thaddeus Shannon, Portland State University
Robert Daasch, Portland State University
pp. 427-432
Dhruva Acharyya, University of Maryland at Baltimore County
Jim Plusquellic, University of Maryland at Baltimore County
pp. 433-438
Mehrdad Nourani, University of Texas at Dallas
Mohammad Tehranipoor, University of Maryland at Baltimore County,
Nisar Ahmed, Texas Instruments
pp. 439-444
12C: IP Session - On the Way from DFT to DFM...Looking for Systematic Marginalities
13A: Panel Session - IEEE 1500: Embedded Core-Based Test Standard: Why Should I Adopt It?
13B: Hot Topic Session - Test and DFM: Managing Yield at 90nm and below
13C: Panel Session - Analog TRP: Is Convergence on Horizon?
Author Index
Author Index (PDF)
pp. 453-455
Usage of this product signifies your acceptance of the Terms of Use.