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23rd IEEE VLSI Test Symposium (VTS'05)
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
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Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew, "Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST," VLSI Test Symposium, IEEE, pp. 359-365, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.48,
author = {Peter Wohl and John A. Waicukauski and Sanjay Patel and Cy Hay and Emil Gizdarski and Ben Mathew},
title = {Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {359-365},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.48},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST
SN - 1093-0167
SP359
EP365
A1 - Peter Wohl,
A1 - John A. Waicukauski,
A1 - Sanjay Patel,
A1 - Cy Hay,
A1 - Emil Gizdarski,
A1 - Ben Mathew,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Peter Wohl, Synopsys Inc.
John A. Waicukauski, Synopsys Inc.
Sanjay Patel, Synopsys Inc.
Cy Hay, Synopsys Inc.
Emil Gizdarski, Synopsys Inc.
Ben Mathew, Synopsys Inc.
Scan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution — streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor. SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking.
Citation:
Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew, "Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST," vts, pp.359-365, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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