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23rd IEEE VLSI Test Symposium (VTS'05)
Static Compaction of Delay Tests Considering Power Supply Noise
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
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Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker, "Static Compaction of Delay Tests Considering Power Supply Noise," VLSI Test Symposium, IEEE, pp. 235-240, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.77,
author = {Jing Wang and Xiang Lu and Wangqi Qiu and Ziding Yue and Steve Fancler and Weiping Shi and D. M. H. Walker},
title = {Static Compaction of Delay Tests Considering Power Supply Noise},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {235-240},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.77},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Static Compaction of Delay Tests Considering Power Supply Noise
SN - 1093-0167
SP235
EP240
A1 - Jing Wang,
A1 - Xiang Lu,
A1 - Wangqi Qiu,
A1 - Ziding Yue,
A1 - Steve Fancler,
A1 - Weiping Shi,
A1 - D. M. H. Walker,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Jing Wang, Texas A&M University
Xiang Lu, Texas A&M University
Wangqi Qiu, Texas A&M University
Ziding Yue, Texas A&M University
Steve Fancler, Texas A&M University
Weiping Shi, Texas A&M University
D. M. H. Walker, Texas A&M University
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.
Citation:
Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker, "Static Compaction of Delay Tests Considering Power Supply Noise," vts, pp.235-240, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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