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21st IEEE VLSI Test Symposium
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
Table of Contents
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Plenary Session
Welcome Address
Program Introduction
ITTC: 25 Years of Service
TTTC Naveena Nagi Award
TTEP 2002 Best Tutorial Award
Session 1A: New Directions in Scan Test
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Samitha Samaranayake, Massachusetts Institute of Technology
Emil Gizdarski, Synopsys Inc.
Nodari Sitchinava, Massachusetts Institute of Technology
Frederic Neuveux, Synopsys Inc.
Rohit Kapur, Synopsys Inc.
T. W. Williams, Synopsys Inc.
pp. 9
Session 1B: Outlier Identification & Current Based Test
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IP Session 1C: How to Get to Open Architecture ATE?
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Assuring Signal Integrity Exists in an Open Architecture
Scalability Challenges in Open Architecture ATE
Open Architecture Testers: The Value Proposition for User's
Session 2A: Advances in Built-In Self-Test - I
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Grzegorz Mrugalski, Poznan University of Technology
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
pp. 57
Session 2B: Analog and Mixed-Signal Test - I
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Marcelo Negreiros, Universidade Federal do Rio Grande do Sul - UFRGS
Luigi Carro, Universidade Federal do Rio Grande do Sul - UFRGS
Altamiro Amadeu Susin, Universidade Federal do Rio Grande do Sul - UFRGS
pp. 77
Hak-soo Yu, The University of Texas at Austin
Sungbae Hwang, The University of Texas at Austin
Jacob A. Abraham, The University of Texas at Austin
pp. 83
IP Session 2C: Silicon Proven IP Cores
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The Testing and Qualification of ARM Cores
Qualification and Test for Embedded Memory IP
Requirements and Challenges for Silicon-Proven Libraries
Session 3A: Test Compaction
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Session 3B: Testing Buses and On-Chip Interconnect
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E. Cota, PPGC - Inst. de Inform?tica
M. Kreutz, PPGC - Inst. de Inform?tica
C.A. Zeferino, PPGC - Inst. de Inform?tica; Centro de Ci?ncias Tecnol?gicas da Terra e do Mar - Univali
L. Carro, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
M. Lubaszewski, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
A. Susin, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
pp. 128
IP Session 3C: Test and Diagnosis of ICs Using 130 nm & 90 nm Technologies
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Defect Screening & Failure Analysis in 90nm
Test Cost Challenges: Test Foundry Business Perspective
Solutions for 'New' Problems, for 130nm and Beyond
Session 4A: Test Challenges in Nanometer Technologies
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M. H. Tehranipour, The University of Texas at Dallas
N. Ahmed, The University of Texas at Dallas
M. Nourani, The University of Texas at Dallas
pp. 158
IP Session 4C: Test Data Analysis
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Analysis of "Partial Open" Defects - Are Delay Failures More Likely with Copper Interconnects?
Facts Unmask Culprits: Process Monitoring Using Test Data
Yield Improvement through Statistical Analysis of Test Data
Special Session 5A: Panel
Is Open Architecture the Future of ATE?
Special Session 5B: Panel
Emerging Technology: Challenges in the Fabrication and Test of DNA Microarray Based Bio-chips
Session 6A: Advanced Test Generation and Fault Simulation Techniques
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Aiman El-Maleh, King Fahd University of Petroleum and Minerals
Khaled Al-Utaibi, King Fahd University of Petroleum and Minerals
pp. 179
Session 6B: Analog and Mixed-Signal Test - 2
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Chauchin Su, National Chiao Tung University
Chih-Hu Wang, National Central Univ.
Wei-Juo Wang, National Central Univ.
IS Tseng, Chroma ATE Inc.
pp. 197
Mani Soma, University of Washington, Seattle
Welela Haileselassie, University of Washington, Seattle
Jessica Sherrid, University of Washington, Seattle
pp. 203
IP Session 6C: Testing High Speed I/Os
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PCI Express and Hypertransport: Examples for the Test Challenges and Solutions of Today's High-Speed IO Interfaces
A Low Cost, Accurate, I/O Test Methodology
Don't Touch Those Pins! Manufacturing Test for High Speed Serial Interfaces
Session 7A: Test Data Compression
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Session 7B: Memory Testing
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Said Hamdioui, Intel Corporation; Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Mike Rodgers, Intel Corporation
pp. 241
Chih-Wea Wang, National Tsing Hua University
Kuo-Liang Cheng, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 248
IP Session 7C: ATE Facilities for Modular SoC Testing
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Potential Applications for Multi-Port ATE
Cost-Effective SoC Core-Based Yield Tracking
The Role of a DfT-Focused Tester in SoC Validation
Session 8A: Power Consumption and Test
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Dan Zhao, State University of New York at Buffalo
Shambhu Upadhyaya, State University of New York at Buffalo
pp. 273
Xiaoyun Sun, University of Minnesota
Larry Kinney, University of Minnesota
Bapiraju Vinnakota, University of Minnesota
pp. 279
Session 8B: Testing Core-Based SoCs
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Tomokazu Yoneda, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 287
IP Session 8C: Layout Driven Design for Test & Manufacturability
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Design for Yield and Manufacturability through Integrated Yield Optimization
Layout Driven TAM and Scan Chain Optimization
Modeling Yield Improvement Objectives in Compaction Tools
Special Session 9A: Panel
Future Vision for ATE Software
Special Session 9B: Panel
Embedded Tutorial: Yield & Repair Analysis
Special Session 9C: Panel
Session 10A: System-Level Test Issues
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Erik Larsson, Linkopings Universitet; Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 319
Wei Zou, University of Iowa
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, Purdue University
Yu Huang, Mentor Graphics Corporation
pp. 325
Session 10B: Diagnosis Techniques
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Angela Krstic, University of California, Santa Barbara
Li-C. Wang, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
Jing-Jia Liou, National Tsing-Hua University, Taiwan
pp. 339
Ananta K. Majhi, Philips Research Laboratories
Guido Gronthoud, Philips Research Laboratories
Camelia Hora, Philips Research Laboratories
Maurice Lousberg, Philips Research Laboratories
Pop Valer, Univ. of Twente
Stefan Eichenberger, Philips Semiconductors
pp. 345
Session 11A: Advances in Built-In Self-Test - 2
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Takahisa Hiraide, Fujitsu Laboratories Ltd.
Kwame Osei Boateng, Fujitsu Laboratories Ltd.
Hideaki Konishi, Fujitsu Ltd.
Koichi Itaya, Fujitsu Ltd.
Michiaki Emori, Fujitsu Ltd.
Hitoshi Yamanaka, Fujitsu Ltd.
Takashi Mochiyama, Fujitsu Ltd.
pp. 359
Session 11B: Test in the Presence of Bridging Faults
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Zhuo Li, Texas A&M University
Xiang Lu, Texas A&M University
Wangqi Qiu, Texas A&M University
Weiping Shi, Texas A&M University
D. M. H. Walker, Texas A&M University
pp. 379
Shahdad Irajpour, University of Southern California
Shahin Nazarian, University of Southern California
Lei Wang, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 385
IP Session 11C: SoC Test Practices for Consumer Products
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Test Point Insertion Methods to Reduce Test Application Time for SoCs
Design and Test of a SoC Design with Built-In Redundancy Allocation of SRAMs
A Practical Design of At-Speed Logic BIST for Large SoCs
Session 12A: Emerging Circuit Technologies: Test Challenges
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Ketan N. Patel, University of Michigan
John P. Hayes, University of Michigan
Igor L. Markov, University of Michigan
pp. 410
Jing-ling Yang, The University of Hong Kong
Chiu-sing Choy, The Chinese University of Hong Kong
Cheong-fat Chan, The Chinese University of Hong Kong
Kong-pong Pun, The Chinese University of Hong Kong
pp. 417
IP Session 12C: P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data
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Using DFT Disclosure Information for Economic Merging of Soft Cores
Generic Programmable Memory BIST for Testing Custom Embedded Memories in High Performance Microprocessors
A Case Study in Test Integration of Soft Cores in a Complex SoC Design Using DFT Disclosure Document
Special Session 13A: Panel
Hot Topic: ITRS Roadmap 2003
Special Session 13B: Panel
Designing with Unreliable Components
Special Session 13C: Panel
Speed Test and Performance Validation
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