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19th IEEE VLSI Test Symposium
Marina Del Rey, CA
March 29-April 03
ISBN: 0-7695-1122-8
Table of Contents
Keynote Address
Invited Presentation
Session 1: BIST Techniques
M. Psarakis, University of Athens
A. Paschalis, University of Athens
N. Kranitis, University of Athens
D. Gizopoulos, University of Piraeus
Y. Zorian, LogicVision Inc.
pp. 0015
Session 2: Diagnosis Methods
Session 3: Test Data Compression
Aiman El-Maleh, King Fahd University of Petroleum and Minerals
Esam Khan, King Fahd University of Petroleum and Minerals
Saif al Zahir, University of British Columbia
pp. 0054
Session 4: Sythesis & Design for Testability
Kelly Ockunzzi, Case Western Reserve University
Chris Papachristou, Case Western Reserve University
pp. 0075
Session 5: Scan Chain Design
Session 6: Innovative Measurement Techniques
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd
Masahiro Ishida, Advantest Laboratories, Ltd
Mani Soma, University of Washington
David Halter, Motorola Inc.
Rajesh Raina, Motorola Inc.
Jim Nissen, Motorola Inc.
pp. 0102
Session 7: Diagnosis & Verification ATPG
Session 8: Defect Analysis and IDDx Diagnosis
Antonio Zenteno, National Institute for Astrophysics, Optics and Electronics-INAOE
Victor H. Champac, National Institute for Astrophysics, Optics and Electronics-INAOE
pp. 0138
Chintan Patel, University of Maryland Baltimore County
Jim Plusquellic, University of Maryland Baltimore County
pp. 0145
Special Session 1: Panel
Special Session 2: Hot Topic Session
Session 9: SOC Testing
Session 10: Online Testing
E.S. Sogomonyan, Russian Academy of Science
A. Morosov, Potsdam University
J. Rzeha, Potsdam University
M. Gossel, Potsdam University
A. Singh, Auburn University
pp. 0184
Session 11: Self-Test Techniques
Jing-Reng Huang, University of California, Santa Barbara
Madhu K. Iyer, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
pp. 0198
Wei-Cheng Lai, University of California, Santa Barbara
Jing-Reng Huang, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
pp. 0204
Session 12: Memory Testing
Session 13: Scalable Fault Simulation, Model Build and ATPG Methods
Ozgur Sinanoglu, University of California, San Diego
Alex Orailoglu, University of California, San Diego
pp. 0240
Yiorgos Makris, Yale University
Vishal Patel, University of California, San Diego
Alex Orailoglu, University of California, San Diego
pp. 0246
Session 14: Test Stimulus Generation for Analog Testing
Yue-Tsang Chen, Chung Shan Institute of Science and Technology
Chauchin Su, National Central University
pp. 0260
F. Azaïs, University of Montpellier
S. Bernard, University of Montpellier
Y. Bertrand, University of Montpellier
X. Michel, University of Montpellier
M. Renovell, University of Montpellier
pp. 0266
Eduardo J. Peralías, Universidad de Sevilla
Gloria Huertas, Universidad de Sevilla
Adoración Rueda, Universidad de Sevilla
José L. Huertas, Universidad de Sevilla
pp. 0272
Special Session 3: Hot Topic Session
Special Session 4: Embedded Tutorial
Special Session 5: Panel
Session 15: Memory Diagnosis
I. de Paúl, University Illes Balears
M. Rosales, University Illes Balears
B. Alorda, University Illes Balears
J. Segura, University Illes Balears
C. Hawkins, The University of New Mexico
J. Soden, Sandia National Labs
pp. 0286
John T. Chen, Carnegie Mellon University
Wojciech Maly, Carnegie Mellon University
Janusz Rajski, Mentor Graphics Corporation
Omar Kebichi, Mentor Graphics Corporation
Jitendra Khare, Intel Corporation-Sacramento
pp. 0292
Session 16: Minimizing Test Power
Session 17: Estimating and Reducing Infant Mortality
Chao-Wen Tseng, Stanford University
Ray Chen, Stanford University
Edward J. McCluskey, Stanford University
Phil Nigh, IBM MicroElectronics
pp. 0339
Session 18: Novel ATPG Techniques
Yi-Shing Chang, University of Southern California
Sandeep Gupta, University of Southern California
Melvin Breuer, University of Southern California
pp. 0358
Session 19: Test Scheduling, Leakage Estimation and Onchip Delay Measurement
Session 20: Fault Modeling and BIST Evaluation
Ginette Monté, Ecole Polytechnique de Montr?al
Bernard Antaki, Ecole Polytechnique de Montr?al
Serge Patenaude, Ecole Polytechnique de Montr?al
Yvon Savaria, Ecole Polytechnique de Montr?al
Claude Thibeault, Ecole de Technologie Sup?rieure de Montr?al
Pieter Trouborst, Nortel Networks
pp. 0388
Keerthi Heragu, Texas Instruments Inc.
Manish Sharma, University of Illinois
Rahul Kundu, Carnegie Mellon University
R.D. (Shawn) Blanton, Carnegie Mellon University
pp. 0396
Special Session 6: Showcase
Special Session 7: Panel
Special Session 8: Panel
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