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19th IEEE VLSI Test Symposium
Resistive Opens in a Class of CMOS Latches: Analysis and DFT
Marina Del Rey, CA
March 29-April 03
ISBN: 0-7695-1122-8
| ASCII Text | x | ||
| Antonio Zenteno, Victor H. Champac, "Resistive Opens in a Class of CMOS Latches: Analysis and DFT," VLSI Test Symposium, IEEE, pp. 0138, 19th IEEE VLSI Test Symposium, 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/VTS.2001.923430, author = {Antonio Zenteno and Victor H. Champac}, title = {Resistive Opens in a Class of CMOS Latches: Analysis and DFT}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0138}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923430}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Test Symposium, IEEE TI - Resistive Opens in a Class of CMOS Latches: Analysis and DFT SN - 0-7695-1122-8 SP EP A1 - Antonio Zenteno, A1 - Victor H. Champac, PY - 2001 VL - 0 JA - VLSI Test Symposium, IEEE ER - | |||
The behavior of a class of CMOS latches in the presence of resistive opens is investigated. The detectability of resistive opens by delay testing is analyzed. The resistive opens in the driver and inverter stages are classified according to its behavior. Opens in conducting paths, single open gates and multiple open gates. Opens in conducting paths are the easiest to detect and opens in single open gates are the most difficult to detect. Resistive opens in the clocked inverter deserves an special attention. Some open location in this stage are well known as undetectable by a traditional voltage test. A DFT (Design for Testability) approach is proposed for opens in conducting paths of the clocked inverter stage. The cost of the DFT approach in terms of speed degradation and area overhead is evaluated. A comparison is made with other testable latches structures proposed in the literature. Other two interesting cases of opens in the clocked inverter have been found.
Citation:
Antonio Zenteno, Victor H. Champac, "Resistive Opens in a Class of CMOS Latches: Analysis and DFT," vts, pp.0138, 19th IEEE VLSI Test Symposium, 2001
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