Apr. 30, 2000 to May 4, 2000
Li Chen , University of California at San Diego
Sujit Dey , University of California at San Diego
At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high-test overhead.In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead.
At-speed testing, self-test, microprocessor, instructions, structural testing
Li Chen, Sujit Dey, "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors", VTS, 2000, 2013 IEEE 31st VLSI Test Symposium (VTS), 2013 IEEE 31st VLSI Test Symposium (VTS) 2000, pp. 255, doi:10.1109/VTEST.2000.843853