• V
  • VTS
  • 1997
  • 15th IEEE VLSI Test Symposium (VTS'97)
Advanced Search 
15th IEEE VLSI Test Symposium (VTS'97)
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
Table of Contents
KEYNOTE ADDRESS
INVITED TALK
SESSION 1: CORE & PROCESSOR TEST
K. Hatayama, Res. Lab., Hitachi Ltd., Ibaraki, Japan
K. Hikone, Res. Lab., Hitachi Ltd., Ibaraki, Japan
T. Miyazaki, Res. Lab., Hitachi Ltd., Ibaraki, Japan
H. Yamada, Res. Lab., Hitachi Ltd., Ibaraki, Japan
pp. 17
SESSION 2: RAM TEST
H. Goto, Fac. of Eng., Chiba Univ., Japan
S. Nakamura, Fac. of Eng., Chiba Univ., Japan
K. Iwasaki, Fac. of Eng., Chiba Univ., Japan
pp. 31
A.J. van de Goor, Delft University of Technology
I.B.S. Tlili, Delft University of Technology
pp. 37
SESSION 3: BIST I
S. Chiusano, Dipt. di Autom. e Inf., Politecnico di Torino, Italy
F. Corno, Dipt. di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipt. di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipt. di Autom. e Inf., Politecnico di Torino, Italy
pp. 60
SESSION 4: CURRENT TESTING TECHNIQUES
R. Rodriguez-Montanes, Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras, Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 68
Yiming Gong, Quickturn Syst. Inc., Mountain View, CA, USA
S. Chakravarty, Quickturn Syst. Inc., Mountain View, CA, USA
pp. 74
SESSION 5: DELAY TEST & DIAGNOSIS
Liang-Chi Chen, Electrical Engineering -- Systems University of Southern California, CA, USA
Sandeep K. Gupta, Electrical Engineering -- Systems University of Southern California, CA, USA
Melvin A. Breuer, Electrical Engineering -- Systems University of Southern California, CA, USA
pp. 88
P. Girard, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
V. Moreda, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 94
X.T. Chen, Texas A & M University
F.J. Meyer, Texas A & M University
F. Lombardi, Texas A & M University
pp. 101
SESSION 6: FAULT MODELING & PARAMETRIC TEST
Yi-Shing Chang, Electrical Engineering - Systems University of Southern California, Los Angeles
Sandeep K. Gupta, Electrical Engineering - Systems University of Southern California, Los Angeles
Melvin A. Breuer, Electrical Engineering - Systems University of Southern California, Los Angeles
pp. 110
P. Dahlgren, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 117
SESSION 7: VERIFICATION & DEBUGGING
P. Wohl, Adv. Test Technol. Inc., Williston, VT, USA
J. Waicukauski, Adv. Test Technol. Inc., Williston, VT, USA
pp. 130
Rathish Jayabharathi, Design Technology - Logic Test Technology Intel Corporation, Folsom, CA
Kyung Tek Lee, Computer Engineering Research Center University of Texas at Austin, Austin, TX
Jacob A. Abraham, Computer Engineering Research Center University of Texas at Austin, Austin, TX
pp. 137
Shi-Yu Huang, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kuang-Chien Chen, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 143
Martin Keim, Institute of Computer Science Albert-Ludwigs-University
Michael Martin, Institute of Computer Science Albert-Ludwigs-University
Bernd Becker, Institute of Computer Science Albert-Ludwigs-University
Rolf Drechsler, Institute of Computer Science Albert-Ludwigs-University
Paul Molitor, Institute of Computer Science Albert-Ludwigs-University
pp. 150
SESSION 8: ANALOG TEST 1
Zbigniew Jaworski, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Mariusz Niewczas, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Wieslaw Kuzmicz, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
pp. 172
N.J. Godambe, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
C.-J.R. Shi, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 177
PANEL SESSION 1:
PANEL SESSION 2
SESSION 9: SEQUENTIAL CIRCUITS TEST I
Michael S. Hsiao, Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Elizabeth M. Rudnick, Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
Janak H. Patel, Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL http://www.crhc.uiuc.edu/
pp. 188
A. Khoche, Sunrise Test Syst., Fremont, CA, USA
E. Brunvand, Sunrise Test Syst., Fremont, CA, USA
pp. 203
SESSION 10: CONCURRENT CHECKING
C. Metra, Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli, Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco, Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 210
X. Kavousianos, Dept. of Comput. Eng. & Inf., Patras Univ., Greece
D. Nikolos, Dept. of Comput. Eng. & Inf., Patras Univ., Greece
pp. 216
V.A. Vardanian, Armenian Nat. Academy of Sci., American Univ. of Armenia, Yerevan, Armenia
pp. 222
SESSION 11: TEST OF REGULAR STRUCTURES
M. Renovell, LIRMM-UM, Montpellier, France
J. Figueras, LIRMM-UM, Montpellier, France
Y. Zorian, LIRMM-UM, Montpellier, France
pp. 230
Dimitris Gizopoulos, Institute of Informatics & Telecommunications, NCSR Athens, GREECE
Mihalis Psarakis, Institute of Informatics & Telecommunications, NCSR Athens, GREECE
Antonis Paschalis, Institute of Informatics & Telecommunications, NCSR Athens, GREECE
pp. 238
C.A. Fleischer, Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
L.A. Belfore, II, Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
pp. 245
SESSION 12: ANALOG TEST II
Christian Dufaza, Laboratoire d'Informatique de Robotique
Hassan Ihs, Laboratoire d'Informatique de Robotique
pp. 252
P.N. Variyam, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjeee, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
N. Nagi, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 261
Soon Jyh Chang, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu E Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 267
SESSION 13: FAULT SIMULATION AND REDUNDANCY IDENTIFICATION
D. Krishnaswamy, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
P. Banerjee, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 274
Laura Farinetti, Dip. di Automatica e Informatica, Politecnico di Torino
Pier Luca Montessoro, Dip. di Ingegneria Elettrica, Gestionale e Meccanica Universita` degli Studi di Udine
pp. 282
J.-K. Zhao, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 288
SESSION 14: MIXED SIGNAL TEST
W. Verhaegen, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
G. Van der Plas, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
G. Gielen, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
pp. 296
Eduardo Peralias, Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
Adoracion Rueda, Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
Jose L. Huertas, Instituto de Microelectr_nica de Sevilla (IMSE-CNM) email: rueda@cnm.us.es
pp. 302
PANEL SESSION 3:
PANEL SESSION 4:
PANEL SESSION 5:
SESSION 15: SEQUENTIAL CIRCUITS TEST II
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 329
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 336
SESSION 16: ON-LINE TESTING AND FAULT-TOLERANT DESIGN
J. Yeandel, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
D. Thulborn, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
S. Jones, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
pp. 344
A. Hlawiczka, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
M. Gossel, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
E.S. Sogormonyan, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
pp. 350
G. Buonanno, Dipt. di Elettronica, Politecnico di Milano, Italy
M. Pugassi, Dipt. di Elettronica, Politecnico di Milano, Italy
M.G. Sami, Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 356
SESSION 17: SCAN AND BOUNDARY SCAN
S.R. Maka, Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA
pp. 364
SESSION 18: TESTABILITY ANALYSIS
A. Jee, Semicond.. Diagnosis & Test, Mipitas, CA, USA
F.J. Ferguson, Semicond.. Diagnosis & Test, Mipitas, CA, USA
pp. 384
J. Savir, Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 399
SESSION 19: BIST II
J. Savir, Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 416
Can Oekmen, Institute of Computer Science Albert-Ludwigs-University
Martin Keim, Institute of Computer Science Albert-Ludwigs-University
Rolf Krieger, Institute of Computer Science Albert-Ludwigs-University
Bernd Becker, Institute of Computer Science Albert-Ludwigs-University
pp. 426
SESSION 20: THERMAL & ELEVATED VOLTAGE TESTING
Josep Altet, Universitat Politecnica de Catalunya
Antonio Rubio, Universitat Politecnica de Catalunya
pp. 434
V. Szekely, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
M. Rencz, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
B. Courtois, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 440
J.T.Y. Chang, Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA
pp. 446
PANEL SESSION 6:
Thermal Testing: Why Do We Need it?
PANEL SESSION 7:
PANEL SESSION 8:
Usage of this product signifies your acceptance of the Terms of Use.