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15th IEEE VLSI Test Symposium (VTS'97)
Polynomial Formal Verification of Multipliers
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
| ASCII Text | x | ||
| Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor, "Polynomial Formal Verification of Multipliers," VLSI Test Symposium, IEEE, pp. 150, 15th IEEE VLSI Test Symposium (VTS'97), 1997. | |||
| BibTex | x | ||
| @article{ 10.1109/VTEST.1997.599468, author = {Martin Keim and Michael Martin and Bernd Becker and Rolf Drechsler and Paul Molitor}, title = {Polynomial Formal Verification of Multipliers}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {150}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599468}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Test Symposium, IEEE TI - Polynomial Formal Verification of Multipliers SN - 0-8186-7810-0 SP EP A1 - Martin Keim, A1 - Michael Martin, A1 - Bernd Becker, A1 - Rolf Drechsler, A1 - Paul Molitor, PY - 1997 KW - Verification KW - Binary Moment Diagram (BMD) KW - Multiplier VL - 0 JA - VLSI Test Symposium, IEEE ER - | |||
Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became now feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time, when applied to the class of Wallace-tree like multipliers.
Index Terms:
Verification, Binary Moment Diagram (BMD), Multiplier
Citation:
Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor, "Polynomial Formal Verification of Multipliers," vts, pp.150, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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