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14th IEEE VLSI Test Symposium (VTS '96) Princeton, NJ April 28-May 01 ISBN: 0-8186-7304-4 Table of Contents
 | Keynote Address |
 | Invited Talk |
 | Session 1: Design for Testability |
N.A. Touba, Center for Reliable Comput., Stanford Univ., CA, USA pp. 2
R.D. Blanton, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Hayes, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 9
F. Muradali, Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski, Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada pp. 17
K. Heragu, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
V.D. Agrawal, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA pp. 32
 | Session 2: Testability of Analog Circuits |
D. Vazquez, Centro Nacional de Microelectron., Seville Univ., Spain
J.L. Huertas, Centro Nacional de Microelectron., Seville Univ., Spain
A. Rueda, Centro Nacional de Microelectron., Seville Univ., Spain pp. 42
E. Felt, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA pp. 48
M. Renovell, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France
F. Azais, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France
Y. Bertrand, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France pp. 54
M. Ehsanian, Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska, Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
K. Arabi, Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada pp. 60
 | Session 3: Synthesis for Testability |
S. Dey, NEC Res. Inst., Princeton, NJ, USA pp. 74
R. Rochet, Inst. Nat. Polytech. de Grenoble, France pp. 81
R.B. Norwood, Center for Reliable Comput., Stanford Univ., CA, USA pp. 87
Y. Lu, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA pp. 93
M. Miegler, Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
W. Wolz, Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany pp. 99
 | Session 4: IDDQ Testing |
A. Ferre, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras, Univ. Politecnica de Catalunya, Barcelona, Spain pp. 106
W. Maly, Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 112
S.P. Athan, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
D.L. Landis, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
S.A. Al-Arian, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA pp. 118
S. Manich, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras, Univ. Politecnica de Catalunya, Barcelona, Spain pp. 124
H. Balachandran, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D.M.H. Walker, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA pp. 130
 | Session 5: On-Line Testing |
M. Gossel, Inst. of Control Sci., Acad. of Sci., Moscow, Russia pp. 138
C. Metra, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy pp. 145
N. Gaitanis, Inst. of Inf., NCSR "Demokritos", Athens, Greece
A. Paschalis, Inst. of Inf., NCSR "Demokritos", Athens, Greece pp. 151
B. Bose, NEC America Inc., Hillsboro, OR, USA pp. 157
J.-L. Dufour, RAMS Dept., Matra Transp. Int., Montrouge, France pp. 169
 | Session 6: Fault Diagnosis and Dictionaries |
V. Boppana, Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
I. Hartanto, Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
W.K. Fuchs, Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA pp. 174
S. Chakravarty, Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA pp. 192
I. Hartanto, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W. Kent Fuchs, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA pp. 198
W.K. Huang, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
X.T. Chen, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA pp. 204
 | Panel Session 1: |
 | Panel Session 2 |
 | Session 7: Sequential Circuit Testing |
M.S. Hsiao, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA pp. 216
D.E. Long, Sun Microsyst., Menlo Park, CA, USA pp. 224
R.H. Klenke, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.M. Wolf, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA pp. 231
M. Keim, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Stenner, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany pp. 240
J.A. Wehbeh, MIPS Technol. Inc., Mountain View, CA, USA
D.G. Saab, MIPS Technol. Inc., Mountain View, CA, USA pp. 246
 | Session 8: Multi-Chip Modules and Memory Testing |
T.R. Damarla, Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
M.J. Chung, Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
Wei Su, Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
G.T. Michael, Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA pp. 254
B.C. Kim, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
M. Swaminathan, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA pp. 260
G.N. Gaydadjiev, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.G. Mikitjuk, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.N. Yarmolik, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands pp. 272
M.P. Kluth, Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
F. Simon, Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
J.Y. Le Gall, Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
E. Muller, Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc pp. 281
 | Session 9: Delay Fault Testing |
P. Uppaluri, Avant Corp., Research Triangle Park, NC, USA
U. Sparmann, Avant Corp., Research Triangle Park, NC, USA
I. Pomeranz, Avant Corp., Research Triangle Park, NC, USA pp. 288
S. Cremoux, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Fagot, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France pp. 296
V.A. Vardanian, Inst. of Inf. & Autom. Problems, Acad. of Sci., Yerevan, Armenia pp. 302
S. Crepaux-Motte, Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France
M. Jacomino, Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France
R. David, Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France pp. 308
 | Session 10: Non-Traditional Testing |
P. Wohl, Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J. Waicukauski, Microelectron. Div., IBM Corp., Essex Junction, VT, USA
M. Graf, Microelectron. Div., IBM Corp., Essex Junction, VT, USA pp. 324
J.T.-Y. Chang, Center for Reliable Comput., Stanford Univ., CA, USA pp. 332
M. Renovell, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Huc, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France pp. 338
Yuyun Liao, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D.M.H. Walker, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA pp. 344
P. Pant, Georgia Inst. of Technol., Atlanta, GA, USA pp. 354
 | Panel Session 3: |
 | Panel Session 4: |
 | Panel Session 5: |
 | Session 11: Advances in Built-In Self-Test |
M. Soufi, Ecole Polytech. de Montreal, Que., Canada
S. Rochon, Ecole Polytech. de Montreal, Que., Canada
Y. Savaria, Ecole Polytech. de Montreal, Que., Canada pp. 368
D. Kagaris, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA pp. 374
A.P. Stroele, Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany pp. 380
C. Stroud, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
S. Konala, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Ping Chen, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
M. Abramovici, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA pp. 387
N.A. Touba, Center for Reliable Comput., Stanford Univ., CA, USA pp. 393
 | Session 12: Fault Modeling and Defect Coverage |
J. Khare, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
N. Tiday, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 405
P. Dahlgren, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
P. Liden, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden pp. 414
H. Konuk, California Design Center, Hewlett-Packard Co., CA, USA
F.J. Ferguson, California Design Center, Hewlett-Packard Co., CA, USA pp. 422
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S. Kajihara, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA pp. 430
 | Session 13: Fault Simulation and Test Generation |
M.B. Amin, Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota, Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA pp. 438
A. Vergis, Dept. of Comput. Eng., Patras Univ., Greece
C. Tobon, Dept. of Comput. Eng., Patras Univ., Greece pp. 444
W.K. Huang, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA pp. 450
T. Lee, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
I.N. Hajj, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
E.M. Rudnick, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
J.H. Patel, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA pp. 456
D.K. Das, Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India pp. 463
 | Session 14: Mixed-Signal Test Techniques |
H.H. Zheng, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
A. Balivada, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA pp. 470
K. Arabi, Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska, Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada pp. 476
B. Vinnakota, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA pp. 483
Chen-Yang Pan, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA pp. 489
 | Panel Session 6: |
 | Panel Session 7: |
 | Panel Session 8: | Usage of this product signifies your acceptance of the Terms of Use.
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