Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By taking the test strategy into account during the synthesis of the circuit, the overhead due to the test features can be reduced. We present a synthesis-for-scan procedure, called beneficial scan, that orders the scan chain(s) during logic synthesis to minimize the area and performance overhead due to the scan-path by sharing the functional and the test logic. The results show that circuits synthesized with beneficially-ordered scan chains consistently have smaller area and are easier to route than circuits with traditional MUXed flip-flop scan-paths.