Checking experiments to test latches

S.R. Makar; E.J. McCluskey

doi:10.1109/VTEST.1995.512637

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - Checking experiments to test latches

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13th IEEE VLSI Test Symposium (VTS'95)

Checking experiments to test latches

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	S.R. Makar, E.J. McCluskey, "Checking experiments to test latches," VLSI Test Symposium, IEEE, pp. 0196, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512637, author = {S.R. Makar and E.J. McCluskey}, title = {Checking experiments to test latches}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0196}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512637}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Checking experiments to test latches SN - 0-8186-7000-2 SP EP A1 - S.R. Makar, A1 - E.J. McCluskey, PY - 1995 KW - CMOS logic circuits; logic testing; sequential circuits; fault diagnosis; circuit analysis computing; SPICE; finite state machines; integrated circuit testing; exhaustive functional tests; checking experiments; 2-state latches; minimum-length checking; D-latch; simulation; HSpice implementation; transmission gate latch; detectable shorted interconnects; open interconnects; short-to-power faults; short-to-ground faults; stuck open faults; stuck-on faults; pin fault test set; multiplexer-based test set; sequential elements; 2-state state machines; CMOS VL - 0 JA - VLSI Test Symposium, IEEE ER -

S.R. Makar, Center for Reliable Comput., Stanford Univ., CA, USA

E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512637

Abstract: Necessary and sufficient conditions for exhaustive functional tests (checking experiments) of 2-state latches are derived. These conditions are used to derive minimum-length checking experiments. The checking experiment for the D-latch is simulated using an HSpice implementation of the transmission gate latch. All detectable shorted interconnects, open interconnects, short-to-power, short-to-ground, stuck-open, and stuck-on faults are detected. A pin fault test set and a multiplexer-based test set are also simulated. These tests miss some faults detected by the checking experiment.

Index Terms:

CMOS logic circuits; logic testing; sequential circuits; fault diagnosis; circuit analysis computing; SPICE; finite state machines; integrated circuit testing; exhaustive functional tests; checking experiments; 2-state latches; minimum-length checking; D-latch; simulation; HSpice implementation; transmission gate latch; detectable shorted interconnects; open interconnects; short-to-power faults; short-to-ground faults; stuck open faults; stuck-on faults; pin fault test set; multiplexer-based test set; sequential elements; 2-state state machines; CMOS

Citation:

S.R. Makar, E.J. McCluskey, "Checking experiments to test latches," vts, pp.0196, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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