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13th IEEE VLSI Test Symposium (VTS'95)
On shrinking wide compressors
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
| ASCII Text | x | ||
| J. Savir, "On shrinking wide compressors," VLSI Test Symposium, IEEE, pp. 0108, 13th IEEE VLSI Test Symposium (VTS'95), 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/VTEST.1995.512625, author = {J. Savir}, title = {On shrinking wide compressors}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0108}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512625}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Test Symposium, IEEE TI - On shrinking wide compressors SN - 0-8186-7000-2 SP EP A1 - J. Savir, PY - 1995 KW - built-in self test; shift registers; fault diagnosis; logic testing; integrated circuit testing; built-in self-test; multiple-input signature registers; MISRs; wiring overhead; parity; detection probability loss; test length penalty; fault coverage degradation; pseudo-random test VL - 0 JA - VLSI Test Symposium, IEEE ER - | |||
Abstract: Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking a MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.
Index Terms:
built-in self test; shift registers; fault diagnosis; logic testing; integrated circuit testing; built-in self-test; multiple-input signature registers; MISRs; wiring overhead; parity; detection probability loss; test length penalty; fault coverage degradation; pseudo-random test
Citation:
J. Savir, "On shrinking wide compressors," vts, pp.0108, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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