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IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Como, Italy
March 04-March 05
ISBN: 0-7695-0019-6
Table of Contents
Session A: Keynote Address
Session B: Invited Talks
Power Dissipation in the Next Generation Processors
Session C: Embedded Tutorials
Session 1: Low-Power Design Methods and Architectures
Session 2: Posters
M. Delaurenti, Politecnico di Torino
G. Masera, Politecnico di Torino
G. Piccinini, Politecnico di Torino
M. Ruo Roch, Politecnico di Torino
M. Zamboni, Politecnico di Torino
pp. 72
F. Corno, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 78
Carlo Guardiani, SGS-Thomson Microelectronics
Massimo Rossello, SGS-Thomson Microelectronics
Roberto Zafalon, SGS-Thomson Microelectronics
Alberto Macii, Politecnico di Torino
Enrico Macii, Politecnico di Torino
Massimo Poncino, Politecnico di Torino
Riccardo Scarsi, Politecnico di Torino
Cristina Silvano, Universita` di Brescia
pp. 91
Session 3: Power Modeling and Estimation I
S. Bobba, University of Illinois at Urbana-Champaign
I.N. Hajj, University of Illinois at Urbana-Champaign
pp. 116
Session 4: Low-Power Circuits
R. Kanan, Swiss Federal Institute of Technology
M. Declercq, Swiss Federal Institute of Technology
pp. 126
Suhwan Kim, Advanced Computer Architecture Laboratory
Marios C. Papaefthymiou, Advanced Computer Architecture Laboratory
pp. 135
Jesper Steensgaard, The Technical University of Denmark
Un-Ku Moon, Oregon State University
Gabor Temes, Oregon State University
pp. 144
Session 5: Power Modeling and Estimation II
Subodh Gupta, University of Illinois at Urbana-Champaign
Farid N. Najm, University of Illinois at Urbana-Champaign
pp. 164
Marcello Lajolo, Politecnico di Torino
Luciano Lavagno, Politecnico di Torino
Sujit Dey, University of California at San Diego
Alberto Sangiovanni-Vincentelli, University of California at Berkeley
pp. 191
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