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2010 23rd International Conference on VLSI Design
Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer
Bangalore, India
January 03-January 07
ISBN: 978-0-7695-3928-7
| ASCII Text | x | ||
| Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti, "Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer," VLSI Design, International Conference on, pp. 164-169, 2010 23rd International Conference on VLSI Design, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/VLSI.Design.2010.75, author = {Abinesh Ramachandran and Bharghava Rajaram and Suresh Purini and Govindarajulu Regeti}, title = {Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2010}, issn = {1063-9667}, pages = {164-169}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.75}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Design, International Conference on TI - Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer SN - 1063-9667 SP164 EP169 A1 - Abinesh Ramachandran, A1 - Bharghava Rajaram, A1 - Suresh Purini, A1 - Govindarajulu Regeti, PY - 2010 KW - low power KW - block data transfer KW - bus encoding KW - error detection VL - 0 JA - VLSI Design, International Conference on ER - | |||
In this work the authors propose a data coding protocol that leads to power reduction for block data transfer in off-chip buses. I/O pads driving off-chip buses contribute to a major portion of power dissipation in chips. Also, block data transfer is preferred in most systems like caches, DMA etc. In this proposed work, the prior knowledge of the block of data to be transmitted, when it is stored in the buffer, is exploited in a serial fashion to reduce transitions on every bus line. Statistical analysis shows up to 31.9% reduction in transitions. Benchmark results show that it leads to 29% reduction in power consumption. The technique provides added error detection on the lines of parity bit technique, with similar average error detection capability.
Index Terms:
low power, block data transfer, bus encoding, error detection
Citation:
Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti, "Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer," vlsid, pp.164-169, 2010 23rd International Conference on VLSI Design, 2010
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