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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Table of Contents
Introduction
Tutorials
Srivaths Ravi, Texas Instruments, Bangalore, India
Stefan Mangard, Graz Univ. of Technology, Graz, Austria
pp. 3
S. Sundar Kumar Iyer, Indian Institute of Technology Kanpur, Kanpur -208 016, India
Vivek Subramanian, University of California at Berkeley
pp. 4
Praveen Tiwari, Texas Instruments, Banglore, India
Raj Mitra, Texas Instruments, Banglore, India
Manu Chopra, Cadence Design Systems, Noida, India
Alok Jain, Cadence Design Systems, Noida, India
pp. 7
Nikil Dutt, University of California, Irvine
Kaustav Banerjee, University of California, Santa Barbara
Luca Benini, University of Bologna
Kanishka Lahiri, NEC Laboratories, America
Sudeep Pasricha, University of California, Irvine
pp. 8
Eric qBeyne, Kapeldreef 75, 3001 Leuven
pp. 10
Sanjay Gupta, Cadence Design Systems (I) Pvt. Ltd, Noida, India
Taranjit Kukal, Cadence Design Systems (I) Pvt. Ltd, Noida, India
Alok Tripathi, Cadence Design Systems (I) Pvt. Ltd, Noida, India
Raja Mitra, Cadence Design Systems (I) Pvt. Ltd, Noida, India
Ashish Patni, Cadence Design Systems (I) Pvt. Ltd, Noida, India
Siddarth Shetty, Cadence Design Systems (I) Pvt. Ltd, Noida, India
pp. 11
Samarjit Chakraborty, National University of Singapore
Abhik Roychoudhury, National University of Singapore
pp. 13
Plenary Sessions
Session A1: Formal Verification
Shobha Vasudevan, University of Texas at Austin
Vinod Viswanath, Intel Corporation Austin, TX
Jacob A. Abraham, University of Texas at Austin
pp. 43-49
Malay K Ganai, NEC Laboratories America, Princeton, NJ USA
Akira Mukaiyama, NEC, Tokyo, Japan
Aarti Gupta, NEC Laboratories America, Princeton, NJ USA
Kazutoshi Wakabayshi, NEC, Tokyo, Japan
pp. 50-56
S. K. Panda, Indian Institute of Technology, Kharagpur, West Bengal, India
Arnab Roy, Indian Institute of Technology, Kharagpur, West Bengal, India
P. P. Chakrabarti, Indian Institute of Technology, Kharagpur, West Bengal, India
Rajeev Kumar, Indian Institute of Technology, Kharagpur, West Bengal, India
pp. 57-62
Gorschwin Fey, University of Bremen, 28359 Bremen, Germany
Tim Warode, University of Bremen, 28359 Bremen, Germany
Rolf Drechsler, University of Bremen, 28359 Bremen, Germany
pp. 69-76
Session B1: Scheduling for Embedded Processors
F. Li, Pennsylvania State University
G. Chen, Pennsylvania State University
M. Kandemir, Pennsylvania State University
O. Ozturk, Pennsylvania State University
M. Karakoy, Imperial College, UK
R. Ramanarayanan, Pennsylvania State University
B. Vaidyanathan, Pennsylvania State University
pp. 77-82
Pravanjan Choudhury, Indian Institute of Technology Kharagpur, India
P. P. Chakrabarti, Indian Institute of Technology Kharagpur, India
Rajeev Kumar, Indian Institute of Technology Kharagpur, India
pp. 89-94
Sayak Ray, Indian Institute of Technology, Kharagpur, India
Pallab Dasgupta, Indian Institute of Technology, Kharagpur, India
P. P. Chakrabarti, Indian Institute of Technology, Kharagpur, India
pp. 95-102
Session C1: Architecture and Design
Balaji Vaidyanathan, University Park, State College, PA 16802, USA
Wei-Lun Hung, University Park, State College, PA 16802, USA
Feng Wang, University Park, State College, PA 16802, USA
Yuan Xie, University Park, State College, PA 16802, USA
Vijaykrishnan Narayanan, University Park, State College, PA 16802, USA
Mary Jane Irwin, University Park, State College, PA 16802, USA
pp. 103-108
Sanjiv Kumar Mangal, VNIT, Nagpur, Maharashtra, India
Raghavendra B. Deshmukh, VNIT, Nagpur, Maharashtra, India
Rahul M. Badghare, VNIT, Nagpur, Maharashtra, India
R. M. Patrikar, VNIT, Nagpur, Maharashtra, India
pp. 115-120
Sharath Jayaprakash, Michigan State University, East Lansing, MI 48824-1226, U.S.A.
Nihar R. Mahapatra, Michigan State University, East Lansing, MI 48824-1226, U.S.A.
pp. 127-134
Session D1: RF Circuits
R. Bagheri, University of California, Los Angeles
A. Mirzaei, University of California, Los Angeles
S. Chehrazi, University of California, Los Angeles
A. A. Abidi, University of California, Los Angeles
pp. 135-140
Vijay Khawshe, Rambus Bangalore, India
Pravin V Kumar, Rambus Bangalore, India
Renu Rangnekar, Rambus Bangalore, India
Kapil Vyas, Rambus Bangalore, India
Kashi Prabu, Rambus Bangalore, India
Mahabaleshwara, Rambus Bangalore, India
Manish Jain, Rambus Bangalore, India
Navin Mishra, Rambus Bangalore, India
Abhijit Abhyankar, Rambus Bangalore, India
pp. 141-145
Session A2: Technology Modeling and Simulation
Feng Wang, Pennsylvania State University
Yuan Xie, Pennsylvania State University
R. Rajaraman, Pennsylvania State University
B. Vaidyanathan, Pennsylvania State University
pp. 165-170
Hamed Aminzadeh, Ferdowsi University of Mashhad
Mohammad Danaie, Ferdowsi University of Mashhad
Reza Lotfi, Ferdowsi University of Mashhad
pp. 171-176
Yogesh Singh Chauhan, Institute of Microelectronics and Microsystems, Switzerland
Francois Krummenacher, Institute of Microelectronics and Microsystems, Switzerland
Renuad Gillon, AMI Semiconductor (AMIS), Oudenaarde, Belgium
Benoit Bakeroot, University of Ghent, Ghent, Belgium
Michel Declercq, Institute of Microelectronics and Microsystems, Switzerland
Adrian Mihai Ionescu, Institute of Microelectronics and Microsystems, Switzerland
pp. 177-182
Deblina Sarkar, Indian School of Mines, Dhanbad, India
Samiran Ganguly, Indian School of Mines, Dhanbad, India
Deepanjan Datta, Indian School of Mines, Dhanbad, India
A. A. P. Sarab, Indian School of Mines, Dhanbad, India
Sudeb Dasgupta, Indian Institute of Technology, Roorkee
pp. 183-188
M. Jagadesh Kumar, Indian Institute of Technology, New Delhi 110016, India
Vivek Venkataraman, Cornell University, Ithaca, NY
Susheel Nawal, Indian Institute of Technology, New Delhi 110016, India
pp. 189-194
Session B2: Compilation Techniques for Embedded Processors
T. Yemliha, Syracuse University
G. Chen, Pennsylvania State University
O. Ozturk, Pennsylvania State University
M. Kandemir, Pennsylvania State University
pp. 221-226
Neeraj Goel, Indian Institute of Technology Delhi
Anshul Kumar, Indian Institute of Technology Delhi
Preeti Ranjan Panda, Indian Institute of Technology Delhi
pp. 233-238
Rakesh Nalluri, Indian Institute of Technology Delhi
Rohan Garg, Indian Institute of Technology Delhi
Preeti Ranjan Panda, Indian Institute of Technology Delhi
pp. 239-244
L. Xue, Pennsylvania State University
M. Kandemir, Pennsylvania State University
G. Chen, Pennsylvania State University
F. Li, Pennsylvania State University
O. Ozturk, Pennsylvania State University
R. Ramanarayanan, Pennsylvania State University
B. Vaidyanathan, Pennsylvania State University
pp. 251-258
Session C2: Signal Integrity and Timing Analysis
Ashish Dobhal, University of Maryland - College Park.
Vishal Khandelwal, University of Maryland - College Park.
Ankur Srivastava, University of Maryland - College Park.
pp. 259-264
Vineet Wason, Advanced Micro Devices, Sunnyvale, CA, USA
Rajeev Murgai, Fujitsu Laboratories of America, Sunnyvale, CA, USA
WilliamW. Walker, Fujitsu Laboratories of America, Sunnyvale, CA, USA
pp. 271-277
Ratnakar Goyal, Cadence Design Systems, India Pvt. Ltd., Noida, India
Sachin Shrivastava, Cadence Design Systems, India Pvt. Ltd., Noida, India
Harindranath Parameswaran, Cadence Design Systems, India Pvt. Ltd., Noida, India
Parveen Khurana, Cadence Design Systems, India Pvt. Ltd., Noida, India
pp. 278-282
Amit Kumar, Duke University, Durham, NC, USA
Krishnendu Chakrabarty, Duke University, Durham, NC, USA
Chunduri Rama Mohan, Intel Corporation, Folsom, CA, USA
pp. 283-288
Suchismita Roy, Indian Insititute of Technology, Kharagpur
P.P. Chakrabarti, Indian Insititute of Technology, Kharagpur
Pallab Dasgupta, Indian Insititute of Technology, Kharagpur
pp. 295-302
Session D2: Digital Circuits
Keivan Navi, Shahid Beheshti University
Omid Kavehie, Shahid Beheshti University
Mahnoush Rouholamini, Research and Science Center of Hesarak Punak, Tehran, Iran
Amir Sahafi, Research and Science Center of Hesarak Punak, Tehran, Iran
Shima Mehrabi, Research and Science Center of Hesarak Punak, Tehran, Iran
pp. 303-307
Roshan Weerasekera, KTH School for Information and Communication Technology, Sweden
Dinesh Pamunuwa, Lancaster University, Lancaster LA1 4YR, United Kingdom
Li-Rong Zheng, KTH School for Information and Communication Technology, Sweden
Hannu Tenhunen, KTH School for Information and Communication Technology, Sweden
pp. 308-313
Gongqiong Li, Institute of Microelectronics, Tsinghua University, P.R.China
Zhaolin Li, Tsinghua University, P.R.China
pp. 318-323
Sreehari Veeramachaneni, International Institute of Information Technology
Kirthi M Krishna, International Institute of Information Technology
Lingamneni Avinash, International Institute of Information Technology
Sreekanth Reddy Puppala, International Institute of Information Technology
M.B. Srinivas, International Institute of Information Technology
pp. 324-329
Claas Cornelius, University of Rostock
Frank Grassert, University of Rostock
Siegmar Koppe, Advanced Systems and Circuits, Infineon Technologies AG
Dirk Timmermann, University of Rostock
pp. 330-338
Session A3: SOC Test and Verification
Sandeep Jain, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
Jais Abraham, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
Srinivas Kumar Vooka, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
Sumant Kale, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
Amit Dutta, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
Rubin Parekhji, Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India.
pp. 339-344
V.R. Devanathan, ASIC, Texas Instruments India Pvt. Ltd., Bangalore, India
C.P. Ravikumar, ASIC, Texas Instruments India Pvt. Ltd., Bangalore, India
V. Kamakoti, Indian Institute of Technology, Madras, India
pp. 351-356
Rajamani Sethuram, Rutgers University, Piscataway, NJ-08854, USA
Seongmoon Wang, NEC Laboratories America, Princeton, NJ-08540, USA
Srimat T. Chakradhar, NEC Laboratories America, Princeton, NJ-08540, USA
Michael L. Bushnell, Rutgers University, Piscataway, NJ-08854, USA
pp. 357-363
Subir K. Roy, Texas Instruments (India) Pvt. Ltd., C. V. Raman Nagar, Bangalore 560093, India.
Rubin A. Parekhji, Texas Instruments (India) Pvt. Ltd., C. V. Raman Nagar, Bangalore 560093, India.
pp. 364-372
Session B3: Dynamic and Runtime Reconfigurable Systems
Senthil Kumar Lakshmanan, Institute of Integrated Sensor Systems, Kaiserslautern, Germany
Peter Tawdross, Institute of Integrated Sensor Systems, Kaiserslautern, Germany
Andreas Konig, Institute of Integrated Sensor Systems, Kaiserslautern, Germany
pp. 379-384
Jorgen Peddersen, University of New South Wales, Sydney, NSW 2052, Australia
Sri Parameswaran, University of New South Wales, Sydney, NSW 2052, Australia
pp. 385-390
Phillip H. Jones, Washington University, St. Louis, MO
Young H. Cho, Washington University, St. Louis, MO
John W. Lockwood, Washington University, St. Louis, MO
pp. 391-400
Session C3: Synthesis and System Level Design
Dhiren M. Parmar, Indian Institute of Technology
M. Sarma, Indian Institute of Technology
D. Samanta, Indian Institute of Technology
pp. 401-406
K. Najeeb, Indian Institute of Technology Madras
Karthik Gururaj, Indian Institute of Technology Madras
V. Kamakoti, Indian Institute of Technology Madras
Vivekanand M Vedula, Intel Corporation Austin, TX
pp. 407-412
Session D3: Low Power
Hendrik F. Hamann, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Alan Weger, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
James Lacey, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Zhigang Hu, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Pradip Bose, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Erwin Cohen, IBM Systems and Technology Group, Essex Junction, VT, USA
Jamil Wakil, IBM System and Technology Group, Austin, TX, USA
pp. 427-432
Qianneng Zhou, Harbin Institute of Technology, Harbin, China
Fengchang Lai, Harbin Institute of Technology, Harbin, China
Yongsheng Wang, Harbin Institute of Technology, Harbin, China
pp. 433-438
Akepati Sravan, IIT Kharagpur, India
Sujan Kundu, IIT Kharagpur, India
Ajit Pal, IIT Kharagpur, India
pp. 445-450
Yijun Liu, Guangdong University of Technology
Zhenkun Li, Guangdong University of Technology
Pinghua Chen, Guangdong University of Technology
Guangcong Liu, Guangdong University of Technology
pp. 451-458
Session A4: Test Generation and High Level Test
Sreekumar V. Kodakara, University of Minnesota, Minneapolis
Deepak A. Mathaikutty, CESCA, Virginia Tech, Blacksburg, VA
Ajit Dingankar, Intel Corporation,Folsom, CA
Sandeep Shukla, CESCA, Virginia Tech, Blacksburg, VA
David Lilja, University of Minnesota, Minneapolis
pp. 465-472
H. Rahaman, University of Bristol, Bristol BS8 1UB, UK
J. Mathew, University of Bristol, Bristol BS8 1UB, UK
D. K. Pradhan, University of Bristol, Bristol BS8 1UB, UK
pp. 479-484
L. Lingappan, Princeton University, Princeton, NJ
V. Gangaram, Intel Corporation, Folsom, CA
N. K. Jha, Cswitch Inc., Santa Clara, CA
pp. 504-512
Session B4: System Level Modeling, Estimation and Exploration
Nikhil Bansal, NEC Laboratories America, Princeton, NJ
Kanishka Lahiri, NEC Laboratories America, Princeton, NJ
Anand Raghunathan, NEC Laboratories America, Princeton, NJ
pp. 513-520
Ashish Mathur, India Design Center, Freescale Semiconductor
Sourav Roy, India Design Center, Freescale Semiconductor
Rajat Bhatia, India Design Center, Freescale Semiconductor
Arup Chakraborty, India Design Center, Freescale Semiconductor
Vijay Bhargava, India Design Center, Freescale Semiconductor
Jatin Bhartia, India Design Center, Freescale Semiconductor
pp. 521-526
T.S. Rajesh Kumar, Texas Instruments India Ltd., Bangalore, 560 091, India
C.P. Ravikumar, Texas Instruments India Ltd., Bangalore, 560 091, India
R. Govindarajan, Indian Institute of Science
pp. 527-533
Wei-Tsun Sun, University of Auckland, New Zealand
Zoran Salcic, University of Auckland, New Zealand
pp. 534-539
G. Hazari, Indian Institute of Technology Bombay
M. P. Desai, Indian Institute of Technology Bombay
H. Kasture, Indian Institute of Technology Bombay
pp. 540-545
M. Daneshtalab, University of Tehran, Tehran, Iran
A. Pedram, University of Tehran, Tehran, Iran
M. H. Neishaburi, University of Tehran, Tehran, Iran
M. Riazati, University of Tehran, Tehran, Iran
A. Afzali-Kusha, University of Tehran, Tehran, Iran
S. Mohammadi, University of Tehran, Tehran, Iran
pp. 546-550
Nagaraju Pothineni, Indian Institute of Technology, Delhi
Anshul Kumar, Indian Institute of Technology, Delhi
Kolin Paul, Indian Institute of Technology, Delhi
pp. 551-558
Session C4: Power Analysis and Optimization
Aseem Gupta, University of California, Irvine
Nikil D. Dutt, University of California, Irvine
Fadi J. Kurdahi, University of California, Irvine
Kamal S. Khouri, Freescale Semiconductor Inc., Austin, TX
Magdy S. Abadir, Freescale Semiconductor Inc., Austin, TX
pp. 559-564
Subramanian Rajagopalan, Advanced Technology Group, Synopsys India Pvt Ltd
Shabbir Batterywala, Advanced Technology Group, Synopsys India Pvt Ltd
pp. 565-570
Ashish Dobhal, University of Maryland - College Park.
Vishal Khandelwal, University of Maryland - College Park.
Azadeh Davoodi, University of Maryland - College Park.
Ankur Srivastava, University of Maryland - College Park.
pp. 571-576
Ashesh Rastogi, University of Massachusetts, Amherst
Wei Chen, University of Massachusetts, Amherst
Alodeep Sanyal, University of Massachusetts, Amherst
Sandip Kundu, University of Massachusetts, Amherst
pp. 583-588
A. Chattopadhyay, Aachen University of Technology, Germany
D. Zhang, Aachen University of Technology, Germany
D. Kammler, Aachen University of Technology, Germany
E. M. Witte, Aachen University of Technology, Germany
pp. 595-600
Session D4: Memory Design
Masaaki Iijima, Kobe University
Masayuki Kitamura, Kobe University
Masahiro Numa, Kobe University
Akira Tada, Renesas Technology Corp., 4-1, Mizuhara, Itami, Hyogo 664-0005, Japan.
Takashi Ipposhi, Renesas Technology Corp., 4-1, Mizuhara, Itami, Hyogo 664-0005, Japan
pp. 609-614
Qikai Chen, Purdue University, West Lafayette, IN-47907, USA
Arjun Guha, Purdue University, West Lafayette, IN-47907, USA
Kaushik Roy, Purdue University, West Lafayette, IN-47907, USA
pp. 615-620
Duk-Hyung Lee, Kookmin University, Seoul 136-702, Korea
Dong-Kone Kwak, Kookmin University, Seoul 136-702, Korea
Kyeong-Sik Min, Kookmin University, Seoul 136-702, Korea
pp. 632-637
K.R. Viveka, Indian Institute of science, Bangalore-12, India
Abhilasha Kawle, Indian Institute of science, Bangalore-12, India
Bharadwaj Amrutur, Indian Institute of science, Bangalore-12, India
pp. 638-646
Session A5: Emerging Technology
Tao Xu, Duke University, Durham, NC
Krishnendu Chakrabarty, Duke University, Durham, NC
Fei Su, Intel Corporation, Folsom, CA
pp. 647-652
Jyi-Tsong Lin, National Sun Yat-Sen Univ.
Yi-Chuen Eng, National Sun Yat-Sen Univ.
Tai-Yi Lee, National Sun Yat-Sen Univ.
Kao-Cheng Lin, National Sun Yat-Sen Univ.
pp. 653-656
Michael L. Bushnell, Rutgers University
David J., MacDiarmid Institute, U. of Canterbury, New Zealand
Richard J. Blaikie, MacDiarmid Institute, U. of Canterbury, New Zealand
pp. 657-664
Rajiv V. Joshi, IBM T. J. Watson Research Center, Yorktown Heights, NY
Keunwoo Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY
Richard Q. Williams, IBM Technology Group, Essex Junction, VT 05452, U. S. A
Edward J. Nowak, IBM Technology Group, Essex Junction, VT 05452, U. S. A
Ching-Te Chuang, IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 665-672
Session B5: Architecture Enhancements for Embedded Processors
Jiajin Tu, University of Texas at Austin
Jian Chen, University of Texas at Austin
Lizy K.John, University of Texas at Austin
pp. 673-678
Rajamani Sethuram, Rutgers University, Piscataway
Omar I. Khan, Rutgers University, Piscataway
Hari Vijay Venkatanarayanan, Rutgers University, Piscataway
Michael L. Bushnell, Rutgers University, Piscataway
pp. 679-684
Soumyajit Dey, Indian Institute of Technology Kharagpur
Monu Kedia, Indian Institute of Technology Kharagpur
Niket Agarwal, Indian Institute of Technology Kharagpur
Anupam Basu, Indian Institute of Technology Kharagpur
pp. 685-690
Asral Bahari, University of Edinburgh, UK
Tughrul Arslan, University of Edinburgh, UK
Ahmet T. Erdogan, University of Edinburgh, UK
pp. 691-698
Session C5: Process Variation and Reliability
Swarup Bhunia, Case Western Reserve University
Saibal Mukhopadhyay, Purdue University
Kaushik Roy, Purdue University
pp. 699-704
Debayan Bhaduri, Fermat Lab, Virginia Tech
Sandeep Shukla, Fermat Lab, Virginia Tech
Paul Graham, Los Alamos National laboratory
Maya Gokhale, Los Alamos National laboratory
pp. 705-710
Maryam Ashouei, Georgia Institute of Technology
Muhammad M. Nisar, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
Adit D. Singh, Auburn University
Abdulkadir U. Diril, GiQuila Corporation
pp. 711-716
K. Ramakrishnan, Pennsylvania State University, University Park, PA
S. Suresh, Pennsylvania State University, University Park, PA
N. Vijaykrishnan, Pennsylvania State University, University Park, PA
M. J. Irwin, Pennsylvania State University, University Park, PA
pp. 717-722
Xiangning Yang, University of Wisconsin-Madison
Eric Weglarz, University of Wisconsin-Madison
Kewal Saluja, University of Wisconsin-Madison
pp. 723-730
Session D5: Hardware Architectures
Matteo Giaconia, STMicroelectronics, Cornaredo, MI, Italy.
Marco Macchetti, C.E. Consulting (ALTRAN Group), Milan, Italy
Francesco Regazzoni, ALaRI, University of Lugano, Lugano, Switzerland.
Kai Schramm, Horst Gortz Institute for IT Security, Ruhr-Universit at Bochum, Bochum.
pp. 731-737
Kiran K. Gunnam, Texas A&M University, College Station, TX
Gwan S. Choi, Texas A&M University, College Station, TX
Mark B. Yeary, Texas A&M University, College Station, TX
pp. 738-743
M. Sudhakar, International Institute of Information Technology, Hyderabad, Andhra Pradesh, India
R.V. Kamala, International Institute of Information Technology, Hyderabad, Andhra Pradesh, India
M.B. Srinivas, International Institute of Information Technology, Hyderabad, Andhra Pradesh, India
pp. 750-755
J.H Han, University of Edinburgh, UK
A.T Erdogan, University of Edinburgh, UK
T. Arslan, Institute of System Level Integration, Livingston, UK
pp. 756-762
Session A6: Analog Test, Delay Test, and Test Power
Kim T. Le, University of Canberra, Australia
Dong H. Baik, University of Wisconsin-Madison
Kewal K. Saluja, University of Wisconsin-Madison
pp. 769-774
Satish Yada, Indian Institute of Science, Bangalore, India.
Bharadwaj Amrutur, Indian Institute of Science, Bangalore, India.
Rubin A. Parekhji, Texas Instruments (India) Pvt. Ltd., Bangalore, India.
pp. 787-792
Santiago Remersaro, University of Iowa, Iowa City
Xijiang Lin, Mentor Graphics Corporation, Wilsonville, OR
Sudhakar M. Reddy, University of Iowa, Iowa City
Irith Pomeranz, Purdue University, West Lafayette, IN
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
pp. 793-798
Edward Flanigan, Southern Illinois University, Carbondale
Rajsekhar Adapa, Southern Illinois University, Carbondale
Hailong Cui, Qualcomm Incorporated
Michael Laisne, Qualcomm Incorporated
Spyros Tragoudas, Southern Illinois University, Carbondale
Tsvetomir Petrov, Qualcomm Incorporated
pp. 805-812
Session B6: Application-Specific Custom Architectures
Himanshu Patel, MSDG/MRSA, Space Applications Centre (ISRO), Ahmedabad-380 015 .Gujarat. INDIA.
Sanjay Trivedi, MSDG/MRSA, Space Applications Centre (ISRO), Ahmedabad-380 015 .Gujarat. INDIA.
R. Neelkanthan, MSDG/MRSA, Space Applications Centre (ISRO), Ahmedabad-380 015 .Gujarat. INDIA.
V. R. Gujraty, MSDG/MRSA, Space Applications Centre (ISRO), Ahmedabad-380 015 .Gujarat. INDIA.
pp. 819-823
Wei-Feng He, Shanghai Jiao Tong University
Meng-Lian Zhao, Institute of VLSI Design, Zhejiang University, Hangzhou, P.R. China
Chi-Ying Tsui, HKUST, Hong Kong SAR., P.R. China
Zhi-Gang Mao, Microelectronics Center, Harbin Institute of Technology, Harbin, P.R. China
pp. 830-835
Debdeep Mukhopadhyay, Indian Institute of Technology, Kharagpur
Pallavi Joshi, Indian Institute of Technology, Kharagpur
Dipanwita RoyChowdhury, Indian Institute of Technology, Kharagpur
pp. 842-853
V. Amudha, National Institute of Technology, Tiruchirappalli - 620015, India.
B. Venkataramani, National Institute of Technology, Tiruchirappalli - 620015, India.
R. Vinoth kumar, National Institute of Technology, Tiruchirappalli - 620015, India.
S. Ravishankar, National Institute of Technology, Tiruchirappalli - 620015, India.
pp. 848-853
Session C6: Physical Design and Modeling
Gaurav Trivedi, Indian Institute of Technology, Bombay,
Madhav P. Desai, Indian Institute of Technology, Bombay,
H. Narayanan, Indian Institute of Technology, Bombay,
pp. 863-868
Gaurav Trivedi, Indian Institute of Technology, Bombay,
Sumit Punglia, Indian Institute of Technology, Bombay
H. Narayanan, Indian Institute of Technology, Bombay
pp. 869-874
Debjit Sinha, Northwestern University, Evanston, IL
Jianfeng Luo, ATG, Synopsys Inc., Mountain View, CA 94085, USA
Subramanian Rajagopalan, ATG, Synopsys India Pvt. Ltd., Bangalore, India
Shabbir Batterywala, ATG, Synopsys India Pvt. Ltd., Bangalore, India
Narendra V Shenoy, ATG, Synopsys Inc., Mountain View, CA 94085, USA
Hai Zhou, Northwestern University, Evanston, IL
pp. 875-880
Sankar P Debnath, WSG Texas Instruments, Bangalore
Ganesh P Kumar, WSG Texas Instruments, Bangalore
S Jairam, SoCCoE Texas Instruments, Bangalore
pp. 887-892
Pritha Banerjee, Indian Statistical Institute
Susmita Sur-Kolay, Indian Statistical Institute
Arijit Bishnu, Indian Institute of Technology
pp. 893-898
Jin-Tai Yan, Chung-Hua University, Hsinchu, Taiwan, R.O.C
Bo-Yi Chiang, Chung-Hua University, Hsinchu, Taiwan, R.O.C
pp. 899-906
Session D6: Analog Techniques
Reid R. Harrison, University of Utah
Paul T. Watkins, University of Utah
Ryan J. Kier, University of Utah
Daniel J. Black, University of Utah
Robert O. Lovejoy, University of Utah
Richard A. Normann, University of Utah
Florian Solzbacher, University of Utah
pp. 907-912
Sanjay K. Wadhwa, Freescale Semiconductor India Pvt. Ltd.
Deeya Muhury, Freescale Semiconductor India Pvt. Ltd.
Krishna Thakur, Freescale Semiconductor India Pvt. Ltd.
pp. 925-928
Pradipta Patra, Indian Institute of Technology, Kharagpur, India
Amit Patra, Indian Institute of Technology, Kharagpur, India
D. Kastha, Indian Institute of Technology, Kharagpur, India
pp. 935-940
Shantanu A. Bhalerao, Visvesvaraya National Institute of Technology, Nagpur, India
Abhishek V. Chaudhary, Visvesvaraya National Institute of Technology, Nagpur, India
Rajendra M. Patrikar, Visvesvaraya National Institute of Technology, Nagpur, India
pp. 941-946
Author Index
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