Increasing use of embedded memories in modern day System-on-Chip (SoC) designs escalates the need for CAD tools for effective functional verification of memories. We present a new simulator called Natsim for device level digital circuits which can be effectively used for simulation and functional verification of large semiconductor memories and other custom digital circuits. SPICE [6] or switch-level Verilog cannot be effectively used for simulation of memories. Conventional switch level simulators like IRSIM [1], too, typically fail when used for simulating memory circuits, especially SRAM circuits, due to some inherent limitations in their voltage and delay calculation algorithms. We present a technique for voltage and delay calculation which is more robust than the method employed by earlier simulators. We also present a heuristic approach to predict the final logic value at a node in the circuit in presence of MOS transistors with unknown potentials at their gates. We present a methodology for functional verification of memories using Natsim. Experimental results for a wide range of memory circuits have been presented. The work presented in this paper is pending US patent.