Jan. 3, 2006 to Jan. 7, 2006
Peter Caputa , Linköping University
Christer Svensson , Linköping University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.6
We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18 ?m CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.
Peter Caputa, Christer Svensson, "A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency", VLSID, 2006, VLSI Design, International Conference on, VLSI Design, International Conference on 2006, pp. 117-122, doi:10.1109/VLSID.2006.6