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18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)
A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits
Kolkata, India
January 03-January 07
ISBN: 0-7695-2264-5
ASCII Text
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Abhishek Somani, P. P. Chakrabarti, Amit Patra, "A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits," VLSI Design, International Conference on, pp. 535-538, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.
 
 
BibTex
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@article{ 10.1109/ICVD.2005.13,
author = {Abhishek Somani and P. P. Chakrabarti and Amit Patra},
title = {A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2005},
issn = {1063-9667},
pages = {535-538},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.13},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits
SN - 1063-9667
SP535
EP538
A1 - Abhishek Somani,
A1 - P. P. Chakrabarti,
A1 - Amit Patra,
PY - 2005
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Abhishek Somani, Indian Institute of Technology-Kharagpur
P. P. Chakrabarti, Indian Institute of Technology-Kharagpur
Amit Patra, Indian Institute of Technology-Kharagpur
This paper presents a novel method for systematic design of a composite cost function for typical analog circuit sizing optimization problems involving multiple criteria. A non-linear normalization strategy for objective functions has been proposed and has been shown to be better than the traditional linear normalization functions. A Hierarchical Cost Tree Mutation based dynamic weight adjustment algorithm has been developed, which combines the designers? problem specific knowledge with the dynamic solution state in the current iteration to decide the weights in the next iteration. Experiments on a typical Switched Capacitor analog integrator circuit in
Citation:
Abhishek Somani, P. P. Chakrabarti, Amit Patra, "A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits," vlsid, pp.535-538, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005
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