Leakage Reduction techniques in a 0.13um SRAM Cell

Sergey Romanovsky; Wing Leung; Arun Achyuthan; Sreedhar Natarajan

doi:10.1109/ICVD.2004.1260927

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Leakage Reduction techniques in a 0.13um SRAM Cell

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17th International Conference on VLSI Design

Leakage Reduction techniques in a 0.13um SRAM Cell

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung, "Leakage Reduction techniques in a 0.13um SRAM Cell," VLSI Design, International Conference on, pp. 215, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260927, author = {Sergey Romanovsky and Arun Achyuthan and Sreedhar Natarajan and Wing Leung}, title = {Leakage Reduction techniques in a 0.13um SRAM Cell}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {215}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260927}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Leakage Reduction techniques in a 0.13um SRAM Cell SN - 1063-9667 SP EP A1 - Sergey Romanovsky, A1 - Arun Achyuthan, A1 - Sreedhar Natarajan, A1 - Wing Leung, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Sergey Romanovsky, MoSys Incorporated, Kanata, ON, Canada

Arun Achyuthan, MoSys Incorporated, Kanata, ON, Canada

Sreedhar Natarajan, MoSys Incorporated, Kanata, ON, Canada

Wing Leung, MoSys Incorporated, Kanata, ON, Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260927

SRAM standby leakage is very becoming critical with technology scaling to meet the industry's demanding low power requirements.. This paper discusses some of the leakage reduction techniques in a 0.13um SRAM cell in a standard foundry process. Varying the cell bias voltages (VDD, VSS, well biases, bit-line pre-charge, and wordline off) to different standby levels helps achieve reduced leakage. Variation of these bias voltages by 0.3v from normal voltage levels reduces the leakage to 10pA/Cell at room temperature. The VDD and bit-line pre-charge levels need to be restored to at least 95% of the normal level before an active cycle for reliable noise margin. Depending on the bias voltage (VDD or VSS or both) variation, the access time and the static noise margin will be affected. This paper studies the details of critical SRAM cell parameters for different bias voltages variations to reduce standby leakage and their impact to the overall design.

Citation:

Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung, "Leakage Reduction techniques in a 0.13um SRAM Cell," vlsid, pp.215, 17th International Conference on VLSI Design, 2004

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