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New Delhi, India
Jan. 4, 2003 to Jan. 8, 2003
ISBN: 0-7695-1868-0
pp: 183
Vadali Srinivasa Murty , Indian Institute of Technology Madras
P. C. Reghu Raj , Indian Institute of Technology Madras
S. Raman , Indian Institute of Technology Madras
In Natural Language Processing applications, string matching is the main time-consuming operation. A dedicated co-processor for string matching that uses memory interleaving and parallel processing techniques can relieve the host CPU from this burden. This paper reports the FPGA design of such a system with m parallel matching units. It has been shown to improve the performance by a factor of nearly m, without increasing the chip area by more than 45%. The time complexity of the proposed algorithm is O(log<sub>2</sub> n), where n is the number of lexical entries. The memory used by the lexicon has been efficiently organized and the space saving achieved is about 67%.
Approximate match, Perfect match, Memory interleaving, NLP co-processor.
Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman, "DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP", VLSID, 2003, VLSI Design, International Conference on, VLSI Design, International Conference on 2003, pp. 183, doi:10.1109/ICVD.2003.1183134
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