CSDL - Proceedings V

Message from the Program Chairs (PDF)

pp. xvii

VLSI Design and ASPDAC Conference Committee (PDF)

pp. xix

VLSI Design and ASPDAC Technical Program Committee (PDF)

pp. xxi

VLSI Design Steering Committee (PDF)

pp. xxiii

ASPDAC Steering Committee (PDF)

pp. xxiv

VLSI Design 2001 Conference Awards (PDF)

pp. xxvi

Reviewers (PDF)

pp. xxvii

Conference History (PDF)

pp. xxx

Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges (PDF)

Keynote Talks

Biswadip Mitra

pp. 3

LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era (PDF)

Kazuo Yano

pp. 5

Electronic Industry on Fire: How to Survive and Thrive (PDF)

Aart J. de Geus

pp. 6

Digital Watermarking (PDF)

Martin F.H. Schuurmans

pp. 7

Tutorials: Chair: R. A. Parekhji

Functional Verification of System on Chips-Practices, Issues and Challenges (Abstract)

Subir K. Roy, Synplicity, Inc

S. Ramesh, Indian Institute of Technology Bombay

Supratik Chakraborty, Indian Institute of Technology Bombay

Tsuneo Nakata, Fujitsu Laboratories Limited, Japan

Sreeranga P. Rajan, Fujitsu Laboratories of America, USA

pp. 11

PDF

T2: System-Level Design of Embedded Media Systems (PDF)

pp. 14

T3: Trends and Challenges in VLSI Technology Scaling towards 100nm (PDF)

S. Rusu

pp. 16

T4: Mathematical Methods in VLSI (PDF)

pp. 18

T5: Electronic Testing for SOC Designers (PDF)

pp. 20

Specification, Modeling and Design Tools for System-on-Chip (Abstract)

Luciano Lavagno, Cadence Berkeley Laboratories

Sujit Dey, University of California at San Diego

Rajesh Gupta, University of California at Irvine

pp. 21

PDF

T7: MEMS: Technology, Design, CAD and Applications (PDF)

R. Lal

G. Bose

pp. 24

T8: Logic Design of Asynchronous Circuits (PDF)

pp. 26

Session 1A: Low Power I: Chair: Niraj Jha

Evaluating Run-Time Techniques for Leakage Power Reduction (Abstract)

David Duarte, The Pennsylvania State University

Yuh-Fang Tsai, The Pennsylvania State University

Narayanan Vijaykrishnan, The Pennsylvania State University

Mary Jane Irwin, The Pennsylvania State University

pp. 31

PDF

Topological Analysis for Leakage Prediction of Digital Circuits (Abstract)

Wenjie Jiang, Intel Corporation

Vivek Tiwari, Intel Corporation

Erik de la Iglesia, Aplatform Internet Service

Amit Sinha, Massachusetts Institute Of Technology

pp. 39

PDF

Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment (Abstract)

Rahul Kumar, Sasken Communication Technologies Ltd.

C.P. Ravikumar, Texas Instruments India Pvt Ltd

pp. 45

PDF

Estimation of Maximum Power-up Current (Abstract)

Fei Li, University of Wisconsin-Madison

Lei He, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

pp. 51

PDF

Session 2A: Interconnects and Technology I: Chair: V. Visvanathan

Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method (Abstract)

Joong-Ho Kim, Georgia Institute of Technology

Erdem Matoglu, Georgia Institute of Technology

Jinwoo Choi, Georgia Institute of Technology

Madhavan Swaminathan, Georgia Institute of Technology

pp. 59

PDF

Dynamic Noise Analysis with Capacitive and Inductive Coupling (Abstract)

Seung Hoon Choi, Purdue University

Bipul C. Paul, Purdue University

Kaushik Roy, Purdue University

pp. 65

PDF

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models (Abstract)

Makoto Nagata, Hiroshima University

Youichi Nishimori, Hiroshima University

Takashi Morie, Hiroshima University

Atsushi Iwata, Hiroshima University

Yoshitaka Murasaka, A-R-Tec Corp.

pp. 71

PDF

Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis (Abstract)

Yu Cao

pp. 77

PDF

Session 3A: Synthesis I: Chair: Yusuke Matsunaga

An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis (Abstract)

Rupesh S. Shelar, University of Minnesota

Sachin S. Sapatnekar, University of Minnesota

pp. 87

PDF

Design of Asynchronous Controllers with Delay Insensitive Interface (Abstract)

Hiroshi Saito, The Uuniversity of Tokyo

Takashi Nanya, The Uuniversity of Tokyo

Alex Kondratyev, Cadence Design Systems

pp. 93

PDF

Synthesis of High Performance Low Power Dynamic CMOS Circuits (Abstract)

Debasis Samanta, Indian Institute of Technology Kharagpur

Ajit Pal, Indian Institute of Technology Kharagpur

Nishant Sinha, Carnegie Mellon University

pp. 99

PDF

Improvement of ASIC Design Processes (Abstract)

pp. 105

PDF

Session 1B: Low Power II: Chair: A. Raghunathan

ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs (Abstract)

Haris Lekatsas, NEC USA

Joerg Henkel, NEC USA

pp. 113

PDF

Weight-Based Bus-Invert Coding for Low-Power Applications (Abstract)

Rung-Bin Lin, Yuan-Ze University

Chi-Ming Tsai, Yuan-Ze University

pp. 121

PDF

Software-Only Bus Encoding Techniques for an Embedded System (Abstract)

Wei-Chung Cheng, University of Southern California

Jian-Lin Liang, University of Southern California

Massoud Pedram, University of Southern California

pp. 126

PDF

Interconnect Energy Dissipation in High-Speed ULSI Circuits (Abstract)

Payam Heydari, University of California at Irvine

Massoud Pedram, University of Southern California

pp. 132

PDF

Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification (PDF)

Session 2B: Interconnects and Technology II: Chair: Anil Gundurao

pp. 141

Losses in Multilevel Crossover in VLSI Interconnects (Abstract)

P.K. Datta, Indian Institute of Technology, Kharagpur

S. Sanyal, Indian Institute of Technology, Kharagpur

D. Bhattacharya, Indian Institute of Technology, Kharagpur

pp. 142

PDF

Rational ABCD Modeling of High-Speed Interconnects (Abstract)

Qinwei Xu, University of Michigan

Pinaki Mazumder, University of Michigan

pp. 147

PDF

Session 3B: Synthesis II: Chair: Anshul Kumar

Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization (Abstract)

Kuo-Hsing Cheng, Tamkang University

Shun-Wen Cheng, Tamkang University

pp. 155

PDF

A New Synthesis of Symmetric Functions (Abstract)

Hafizur Rahaman, A. P. C. Roy Polytechnic College

Debesh K. Das, Jadavpur University

Bhargab B. Bhattacharya, University of Nebraska-Lincoln

pp. 160

PDF

Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA (Abstract)

Hiroaki Yoshida, University of Tokyo

Hiroaki Yamaoka, University of Tokyo

Makoto Ikeda, University of Tokyo

Kunihiro Asada, University of Tokyo

pp. 166

PDF

D. Sarkar, Indian Institute of Technology at Kharagpur

pp. 172

PDF

Session 1C: Low Power III: Chair: Sujit Dey

A Real Delay Switching Activity Simulator based on Petri net Modeling (Abstract)

Ashok K. Murugavel, University of South Florida

N. Ranganathan, University of South Florida

pp. 181

PDF

Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks (Abstract)

Sanjukta Bhanja, University of South Florida

N. Ranganathan, University of South Florida

pp. 187

PDF

Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits (Abstract)

Debasis Samanta, Indian Institute of Technology Kharagpur

Ajit Pal, Indian Institute of Technology Kharagpur

pp. 193

PDF

Minimizing Energy Consumption for High-Performance Processing (Abstract)

Eric F. Weglarz, University of Wisconsin - Madison

Kewal K. Saluja, University of Wisconsin - Madison

Mikko H. Lipasti, University of Wisconsin - Madison

pp. 199

PDF

Session 2C: Interconnects and Technology III: Chair: G. S. Visweswaran

PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis (Abstract)

A.B. Bhattacharyya, Goa University

Shrutin Ulman, Goa University

pp. 207

PDF

A Parallel and Accelerated Circuit Simulator with Precise Accuracy (Abstract)

pp. 213

PDF

Timing Yield Calculation Using an Impulse-train Approach (Abstract)

Srinath R. Naidu, Eindhoven University of Technology

pp. 219

PDF

Implant Dose Sensitivity of 0.1?m CMOS Inverter Delay (Abstract)

H.C. Srinivasaiah, Indian Institute of Science, Bangalore

Navakanta Bhat, Indian Institute of Science, Bangalore

pp. 225

PDF

Session 3C: Synthesis III: Chair: P. P. Chakrabarti

Exploring the Number of Register Windows in ASIP Synthesis (Abstract)

Vishal P. Bhatt, Synposys India

M. Balakrishnan, Indian Institute of Technology Delhi

Anshul Kumar, Indian Institute of Technology Delhi

pp. 233

PDF

Architecture Implementation Using the Machine Description Language LISA (Abstract)

Oliver Schliebusch, University of Technology Aachen

Andreas Hoffmann, University of Technology Aachen

Achim Nohl, University of Technology Aachen

Gunnar Braun, University of Technology Aachen

Heinrich Meyr, University of Technology Aachen

pp. 239

PDF

A Framework for Design Space Exploration of Parameterized VLSI Systems (Abstract)

Giuseppe Ascia Vincenzo Catania Maurizi Palesi, Universit? di Catania

pp. 245

PDF

An Evolutionary Scheme for Cosynthesis of Real-Time Systems (Abstract)

S. Chakraverty, Netaji Subhas Institute of Technology

C.P. Ravikumar, Texas Instrucments, India

D.Roy Choudhuri, Delhi College of Engineering

pp. 251

PDF

Panel

Entrepreneurship in VLSI: The Next Frontier

Session 4A: Low Power IV: Chair: R. Gupta

Battery-Driven System Design: A New Frontier in Low Power Design (Abstract)

Kanishka Lahiri, University of California at San Diego

Sujit Dey, University of California at San Diego

Debashis Panigrahi, University of California at San Diego

Anand Raghunathan, NEC USA

pp. 261

PDF

A Power Minimization Technique for Arithmetic Circuits by Cell Selection (Abstract)

Masanori Muroyama, Kyushu University

Akihiko Hyodo, Kyushu University

Hiroto Yasuura, Kyushu University

Tohru Ishihara, University of Tokyo

pp. 268

PDF

Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip (Abstract)

Yunsi Fei, Princeton University

Niraj K. Jha, Princeton University

pp. 274

PDF

An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories (Abstract)

Tohru Ishihara, University of Tokyo

Kunihiro Asada, University of Tokyo

pp. 282

PDF

Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories (Abstract)

V. Delaluz, Pennsylvania State University

M. Kandemir, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

M. J. Irwin, Pennsylvania State University

A. Sivasubramaniam, Pennsylvania State University

I. Kolcu, Pennsylvania State University

pp. 288

PDF

Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI (PDF)

Session 5A: Interconnects and Technology IV: Chair: Nagaraj Subramanyam

pp. 297

Transistor Flaring in Deep Submicron-Design Considerations (Abstract)

pp. 299

PDF

A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI (Abstract)

Shuzhou Fang, Tsinghua Uuniversity

Zeyi Wang, Tsinghua Uuniversity

Xianlong Hong, Tsinghua Uuniversity

pp. 305

PDF

Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods (Abstract)

Q. Su, Purdue University

V. Balakrishnan, Purdue University

C-K. Koh, Purdue University

pp. 311

PDF

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches (Abstract)

Maryam Shojaei Baghini, MicroElectronics Group

Madhav P. Desai, MicroElectronics Group

pp. 317

PDF

Session 6A: Synthesis IV: Chair: P. van der Wolf

Embedded Tutorial: General Architectural Concepts for IP Core Re-Use (PDF)

P. Klapproth

pp. 325

Framework for Synthesis of Virtual Pipelines (Abstract)

Srinivasan Dasasathyan, University of Cincinnati

Rajesh Radhakrishnan, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 326

PDF

Automatic Model Refinement for Fast Architecture Exploration (Abstract)

Junyu Peng, University of California at Irvine

Samar Abdi, University of California at Irvine

Daniel Gajski, University of California at Irvine

pp. 332

PDF

Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors (Abstract)

pp. 338

PDF

Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs (Abstract)

Li Shang, Princeton University

Niraj K. Jha, Princeton University

pp. 345

PDF

Session 4B: Analog Design: Chair: Makato Nagata

A Design of Analog C-Matrix Circuits used for Signal/Data Processing (Abstract)

Takayuki Sugawara, Hokkaido University

Yoshikazu Miyanaga, Hokkaido University

Norinobu Yoshida, Hokkaido University

pp. 355

PDF

A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment (Abstract)

Debapriya Sahu, Texas Instruments, Bangalore, India

pp. 360

PDF

Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach (Abstract)

Biranchinath Sahu, Georgia Institute of Technology

Aloke K. Dutta, Indian Institute of Technology

pp. 366

PDF

Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing (Abstract)

Jens Lienig, Robert Bosch GmbH

Goeran Jerke, Robert Bosch GmbH

Thorsten Adler, sci-worx GmbH

pp. 372

PDF

Session 5B: Layout I: Chair: Narendra Shenoy

Buffered Routing Tree Construction Under Buffer Placement Blockages (Abstract)

Wei Chen, University of Southern California

Massoud Pedram, University of Southern California

Premal Buch, Magma Design Automation

pp. 381

PDF

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks (Abstract)

Yuchun Ma, Tsinghua University

Xianlong Hong, Tsinghua University

Sheqin Dong, Tsinghua University

Yici Cai, Tsinghua University

Chung-Kuan Cheng, University of California at San Diego

Jun Gu, University of HongKong

pp. 387

PDF

An Adaptive Interconnect-Length Driven Placer (Abstract)

Chi-Ming Tsai, Yuan-Ze University

Kun-Tien Kuo, Yuan-Ze University

Chyi-Hui Hong, Yuan-Ze University

Rung-Bin Lin, Yuan-Ze University

pp. 393

PDF

Net Clustering Based Macrocell Placement (Abstract)

Stelian Alupoaei, University of South Florida

Srinivas Katkoori, University of South Florida

pp. 399

PDF

Session 6B: Synthesis and Verification: Chair: S. Ramesh

High-Level Synthesis with SIMD Units (Abstract)

Vijay Raghunathan, University of California at Los Angeles

Mani B. Srivastava, University of California at Los Angeles

Milos D. Ercegovac, University of California at Los Angeles

Anand Raghunathan, NEC-USA

pp. 407

PDF

A Heuristic for Clock Selection in High-Level Synthesis (Abstract)

J. Ramanujam, Louisiana State University

Sandeep Deshpande, Louisiana State University

Jinpyo Hong, Louisiana State University

Mahmut Kandemir, The Pennsylvania State University

pp. 414

PDF

Design for Verification at the Register Transfer Level (Abstract)

Indradeep Ghosh, Fujitsu Labs. of America, Inc.

Krishna Sekar, University of California at San Diego

Vamsi Boppana, Zenasis Tech. Inc.

pp. 420

PDF

Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design (Abstract)

G. Nicolescu, TIMA Laboratory

S. Martinez, TIMA Laboratory

L. Kriaa, TIMA Laboratory

W. Youssef, TIMA Laboratory

S. Yoo, TIMA Laboratory

B. Charlot, TIMA Laboratory

A. Jerraya, TIMA Laboratory

pp. 426

PDF

VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme (Abstract)

Session 4C: VLSI Architecture I: Chair: N. Ranganathan

Kavish Seth, Indian Institute Technology at Madras

S. Srinivasan, Indian Institute Technology at Madras

pp. 435

PDF

An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation (Abstract)

Hak-soo Yu, The University of Texas at Austin

Jacob A. Abraham, The University of Texas at Austin

pp. 441

PDF

Architecture and Design of a High Performance SRAM for SoC Design (Abstract)

Shobha Singh, STMicroelectronics

Shamsi Azmi, STMicroelectronics

Nutan Aarawal, STMicroelectronics

Penaka Phani, STMicroelectronics

Ansuman Rout, STMicroelectronics

pp. 447

PDF

VLSI Architecture for a Flexible Motion Estimation with Parameters (Abstract)

Jinku Choi, Waseda University

Masao Yanagisawa, Waseda University

Tatsuo Ohtsuki, Waseda University

Nozomu Togawa, The University of Kitakyushu

pp. 452

PDF

Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language (Abstract)

Prabhat Mishra, University of California at Irvine

Ashok Halambi, University of California at Irvine

Peter Grun, University of California at Irvine

Nikil Dutt, University of California at Irvine

Alex Nicolau, University of California at Irvine

Hiroyuki Tomiyama, ISIT

pp. 458

PDF

Session 5C: Layout II: Chair: Susmita Sur-Kolay

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts (Abstract)

Yukiko Kubo, The University of Kitakyushu

Shigetoshi Nakatake, The University of Kitakyushu

Yoji Kajitani, The University of Kitakyushu

Masahiro Kawakita, Toshiba Corp.

pp. 467

PDF

An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing (Abstract)

Jingyu Xu, Tsinghua University

Xianlong Hong, Tsinghua University

Tong Jing, Tsinghua University

Yici Cai, Tsinghua University

Jun Gu, Hong Kong University of Science & Technology

pp. 473

PDF

Simultaneous Circuit Transformation and Routing (Abstract)

Hiroaki Yoshida, University of Tokyo

Motohiro Sera, University of Tokyo

Masao Kubo, University of Tokyo

Masahiro Fujita, University of Tokyo

pp. 479

PDF

Probabilistic Analysis of Rectilinear Steiner Trees (Abstract)

Chunhong Chen, University of Windsor

pp. 484

PDF

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement (Abstract)

Shiyou Zhao, Purdue University

Kaushik oy, Purdue University

Cheng-Kok Koh, Purdue University

pp. 489

PDF

Session 6C: Test and Validation: Chair: S. P. Rajan

A Novel Method to Improve the Test Efficiency of VLSI Tests (Abstract)

Hailong Cui, University of Nebraska-Lincoln

Sharad C. Seth, University of Nebraska-Lincoln

Shashank K. Mehta, Indian Institute of Technology

pp. 499

PDF

On Test Scheduling for Core-Based SOCs (Abstract)

Sandeep Koranne, Philips Research Labs

pp. 505

PDF

Constraint Driven Pin Mapping for Concurrent SOC Testing (Abstract)

Yu Huang, University of Iowa

Sudhakar M. Reddy, University of Iowa

Nilanjan Mukherjee, Mentor Graphics Corporation

Chien-Chung Tsai, Mentor Graphics Corporation

Omer Samman, Mentor Graphics Corporation

Yahya Zaidan, Mentor Graphics Corporation

Yanping Zhang, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

pp. 511

PDF

Identifying Redundant Wire Replacements for Synthesis and Verification (Abstract)

Katarzyna Radecka, McGill University

Zeljko Zilic, McGill University

pp. 517

PDF

Property-Specific Testbench Generation for Guided Simulation (Abstract)

Aarti Gupta, NEC CCRL

Albert E. Casavant, NEC CCRL

Pranav Ashar, NEC CCRL

Akira Mukaiyama, NEC CCRL

Kazutoshi Wakabayashi, NEC CCRL

X. G. (Sean) Liu, University of California at Santa Barbara

pp. 524

PDF

Session 7A: VLSI Architecture II: Chair: Tohru Ishihara

A New Divide and Conquer Method for Achieving High Speed Division in Hardware (Abstract)

Murali Mohan, Indian Institute Of Technology

Rohini Krishnan, Indian Institute Of Technology

Anshul Kumar, Indian Institute Of Technology

M. Balakrishnan, Indian Institute Of Technology

pp. 535

PDF

Swasad: An Asic Design For High Speed Dna Sequence Matching (Abstract)

Tony Han, University of Queensland

Sri Parameswaran, University of New South Wales

pp. 541

PDF

Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder (Abstract)

M. Palkovic, IMEC

M. Miranda, IMEC

K. Denolf, IMEC

P. Vos, IMEC

F. Catthoor, IMEC

pp. 547

PDF

A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication (Abstract)

Debashis Panigrahi, University of California at San Diego

Clark N. Taylor, University of California at San Diego

Sujit Dey, University of California at San Diego

pp. 553

PDF

Session 8A: Layout III: Chair: B. Bhattacharya

Efficient Macromodeling for On-Chip Interconnects (Abstract)

Qinwei Xu, University of Michigan

Pinaki Mazumder, University of Michigan

pp. 561

PDF

An Upper Bound for 3D Slicing Floorplans (Abstract)

Silke Salewski, University of Hannover

Erich Barke, University of Hannover

pp. 567

PDF

System-Level Point-to-Point Communication Synthesis Using Floorplanning Information (Abstract)

Jingcao Hu, Carnegie Mellon University

Yangdong Deng, Carnegie Mellon University

Radu Marculescu, Carnegie Mellon University

pp. 573

PDF

Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing (Abstract)

Christoph Albrecht, University of Bonn

Andrew B. Kahng, University of California at San Diego

Ion Mandoiu, University of California at San Diego

Alexander Zelikovsky, Georgia State University

pp. 580

PDF

Session 9A: Test I: Chair: Makoto Sugihara

Multiple Faults: Modeling, Simulation and Test (Abstract)

Yong Chang Kim, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

Vishwani D. Agrawal, Agere Systems

pp. 592

PDF

Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch (Abstract)

Subhayu Basu, Princeton University

Debdeep Mukhopadhay, Indian Institute of Technology at Kharagpur

Dipanwita Roychoudhury, Indian Institute of Technology at Kharagpur

Indranil Sengupta, Indian Institute of Technology at Kharagpur

Sudipta Bhawmik, Agere systems

pp. 598

PDF

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST (Abstract)

Nadir Z. Basturkmen, University of Iowa

Sudhakar M. Reddy, University of Iowa

Janusz Rajski, Mentor Graphics Corporation

pp. 604

PDF

Session 7B: Embedded Systems I: Chair: P. Klapproth

Low Power Solution for Wireless Applications (Abstract)

Sornavalli Rarnanathan, Texas Instrwnents India Ltd

Rituparna Mandal, Texas Instrwnents India Ltd

pp. 615

PDF

Address Code and Arithmetic Optimizations for Embedded Systems (Abstract)

J. Ramanujam, Louisiana State University

Satish Krishnamurthy, Louisiana State University

Jinpyo Hong, Louisiana State University

Mahmut Kandemir, The Pennsylvania State University

pp. 619

PDF

Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-chip (SoC) Applications (Abstract)

Yong-Ha Park, Korea Advanced Institute of Science and Technology

Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology

Jeonghoon Kook, Memory R&D Division, Hynix Semiconductor Inc.

pp. 625

PDF

Strategies for Improving Data Locality in Embedded Applications (Abstract)

N. E. Crosbie, Pennsylvania State University

M. Kandemir, Pennsylvania State University

I. Kolcu, UMIST

J. Ramanujam, Louisiana State University

A. Choudhary, Northwestern University

pp. 631

PDF

Session 8B: Layout IV: Chair: Shigetoshi Nakatake

On Routing Demand and Congestion Estimation for FPGAs (Abstract)

Shankar Balachandran, University of Texas at Dallas

Parivallal Kannan, University of Texas at Dallas

Dinesh Bhatia, University of Texas at Dallas

pp. 639

PDF

Layout-driven Timing Optimization by Generalized De Morgan Transform (Abstract)

Supratik Chakraborty, Indian Institute of Technology at Bombay

Rajeev Murgai, Fujitsu Laboratories of America, Inc.

pp. 647

PDF

Reducing Library Development Cycle Time through an Optimum Layout Create Flow (Abstract)

Rituparna Mandal, Texas Instruments India Limited

Dibyendu Goswami, Texas Instruments India Limited

Arup Dash, Texas Instruments India Limited

pp. 655

PDF

A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design (Abstract)

Evangeline F.Y. Young, The Chinese University of Hong Kong

M.L. Ho, The Chinese University of Hong Kong

Chris C.N. Chu, Iowa State University

pp. 661

PDF

Session 9B: Test II: Chair: Ashok Balivada

Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area (Abstract)

Samir Roy, Kalyani Govt. Engineering College

Biplab K Sikdar, Bengal Engineering College

Monalisa Mukherjee, Bengal Engineering College

Debesh K Das, Jadavpur University

pp. 671

PDF

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits (Abstract)

Irith Pomeranz, Purdue University

Sudhakar M. Reddy, University of Iowa

pp. 677

PDF

Optimization of Test Accesses with a Combined BIST and External Test Scheme (Abstract)

Makoto Sugihara, Kyushu University

Hiroto Yasuura, Kyushu University

pp. 683

PDF

Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS) (Abstract)

Niloy Ganguly, IISWBM

Biplab K Sikdar, Bengal Engineering College (D U)

P P al Chaudhuri, Bengal Engineering College (D U)

pp. 689

PDF

Session 7C: Embedded Systems II: Chair: Hiroyuki Tomiyama

Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems (Abstract)

Dexin Li, University of California and Irvine

Pai H. Chou, University of California and Irvine

Nader Bagherzadeh, University of California and Irvine

pp. 697

PDF

Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks (Abstract)

Anupam Datta, Stanford University

Sidharth Choudhury, University of Texas at Austin

Anupam Basu, Indian Institute of Technology Kharagpur

pp. 705

PDF

Input Space Adaptive Embedded Software Synthesis (Abstract)

Weidong Wang, Princeton University

Anand Raghunathan, NEC USA

Ganesh Lakshminarayana, NEC USA

Niraj K. Jha, Princeton Uniersity

pp. 711

PDF

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems (Abstract)

Jiong Luo, Princeton University

Niraj K. Jha, Princeton University

pp. 719

PDF

Session 8C: Verification II: Chair: Hiroto Yasuura

Improved SAT-based Bounded Reachability Analysis (Abstract)

Malay K. Ganai, NEC USA

Adnan Aziz, University of Texas at Austin

pp. 729

PDF

Open Computation Tree Logic for Formal Verification of Modules (Abstract)

Pallab Dasgupta, Indian Institute of Technology, Kharagpur

Arindam Chakrabarti, Indian Institute of Technology, Kharagpur

P.P. Chakrabarti, Indian Institute of Technology, Kharagpur

pp. 735

PDF

RTL-Datapath Verification using Integer Linear Programming (Abstract)

Raik Brinkmann, Siemens AG, Corporate Technology

Rolf Drechsler, University of Bremen

pp. 741

PDF

Verification of an Industrial CC-NUMA Server (Abstract)

Rajarshi Mukherjee, Fujitsu Labora ories of America

Yozo Nakayama, Fujitsu Ltd.

Toshiya Mima, Fujitsu Ltd.

pp. 747

PDF

Session 9C: Test III: Chair: Mike Bushnell

Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting (Abstract)

Sagar Sabade, Texas A&M University

Hank Walker, Texas A&M University

pp. 755

PDF

Divide-and-Conquer IDDQ Testing for Core-based System Chips (Abstract)

C.P. Ravikumar, Texas Instruments India Pvt Ltd

Rahul Kumar, Sasken Communication Technologies Ltd.

pp. 761

PDF

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples (Abstract)

Yun Shao, University of Iowa

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, Purdue University

pp. 767

PDF

Test Solution For OTA Based Analog Circuits (Abstract)

Baidya N ath Ray, Bengal Engineering College ( Deemed University)

P.Pal Chaudhuri, Bengal Engineering College ( Deemed University)

P.K. Nandi, Bengal Engineering College ( Deemed University)

pp. 773

PDF

Special Session: "Hot Chips from India": Chair: S. Karthik

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon (Abstract)

pp. 781

PDF

Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study (Abstract)

Sanjeev Patel, Wipro Technologies

pp. 789

PDF

IEEE 1394a_2000 Physical Layer ASIC (Abstract)

Ranjit Yashwante, ControlNet (India) Pvt. Ltd.

Bhalchandra Jahagirdar, ControlNet (India) Pvt. Ltd.

pp. 795

PDF

Definition, Design and Development of the IXE2424 Network Switch/Router ASIC (PDF)

pp. 801

VLSI Design 2003 Call for Papers (PDF)

pp. 803

ASP-DAC 2003 Call for Papers (PDF)

pp. 804

VDAT 2002 Call for Papers (PDF)

pp. 806

Author Index (PDF)

pp. 807