CSDL - Proceedings V

Message from the Program Chairs (PDF)

pp. xv

Conference Committee (PDF)

pp. xvii

Steering Committee (PDF)

pp. xxi

VLSI Design 2000 Conference Awards (PDF)

pp. xxiii

Reviewers (PDF)

pp. xxv

Conference History (PDF)

pp. xxix

Program Committee (PDF)

pp. xxxi

Keynote Speakers (PDF)

pp. xxxiiii

Tutorials

Optimization and Analysis Techniques for the Deep Submicron Regime (PDF)

pp. 3

Embedded Memories in System Design: Technology, Application, Design and Tools (PDF)

pp. 5

Introduction to SystemC (PDF)

Sudipta Bhawmik

pp. 7

Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies (PDF)

pp. 9

IBM's Blue Logic Design Methodology-Circuits and Physical Design (PDF)

pp. 11

Next Generation Network Processors (PDF)

Deepak Kataria

pp. 13

Functional Verification of Programmable DSP Cores (PDF)

Mahesh Mehendale

Santhosh Kumar Amanna

pp. 16

RealChip, India V. Ranganatha

System Level Testability Issues of Core Based System-on-a-Chip (PDF)

RealChip, India R. Sunda

pp. 18

Tutorial: CMOS Analog Circuits for Wireless Communications (PDF)

pp. 18

Session 1A: Embedded Systems I

Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study (Abstract)

Anupam Rastogi, Indian Institute of Technology

M. Balakrishnan, Indian Institute of Technology

Anshul Kumar, Indian Institute of Technology

pp. 23

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Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures (Abstract)

Kanishka Lahiri, UC San Diego

Sujit Dey, UC San Diego

Anand Raghunathan, NEC USA

pp. 29

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Performance Considerations in Embedded DSP based System-On-a-Chip Designs (Abstract)

Ajit Gupte, Texas Instruments (India) Ltd.

Mahesh Mehendale, Texas Instruments (India) Ltd.

Ramesh Ramamritham, Texas Instruments (India) Ltd.

Deepa Nair, Texas Instruments (India) Ltd.

pp. 36

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Hardware Software Codesign of DSP System Using Grammar Based Approach (Abstract)

A.K. Deb, Royal Institute of Technology

A. Hemani, Royal Institute of Technology

J. Öberg, Royal Institute of Technology

A. Postula, University of Queensland

D. Lindqvist, Ericsson Radio Systems AB

pp. 42

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A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging (Abstract)

Vivek Tiwari, Intel Corp.

pp. 48

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Session 1B: Embedded Systems II

Battery Life Estimation of Mobile Embedded Systems (Abstract)

Debashis Panigrahi, University of California, San Diego

Sujit Dey, University of California, San Diego

Ramesh Rao, University of California, San Diego

Kanishka Lahiri, University of California, San Diego

Carla Chiasserini, Politecnico di Torino

Anand Raghunathan, NEC USA

pp. 57

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Power-aware Multimedia Systems using Run-time Prediction (Abstract)

Pavan Kumar, University of California, Los Angeles

Mani Srivastava, University of California, Los Angeles

pp. 64

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Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language (Abstract)

Prabhat Mishra, University of California, Irvine

Peter Grun, University of California, Irvine

Nikil Dutt, University of California, Irvine

Alex Nicolau, University of California, Irvine

pp. 70

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ASIP Design Methodologies : Survey and Issues (Abstract)

Manoj Kumar Jain, Indian Institute of Technology

M. Balakrishnan, Indian Institute of Technology

Anshul Kumar, Indian Institute of Technology

pp. 76

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Session 1C: SOC Methodologies

ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications (Abstract)

G. Surendra, Indian Institute of Science

S.K. Nandy, Indian Institute of Science

Paul Sathya, STMicroelectronics

pp. 85

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The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes (Abstract)

Vineet Sahula, Regional Engineering College

C.P. Ravikumar, Indian Institute of Technology

pp. 91

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Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique (Abstract)

Anupam Datta, Indian Institute of Technology, Kharagpur

Sidharth Choudhury, Indian Institute of Technology, Kharagpur

Anupam Basu, Indian Institute of Technology, Kharagpur

Hiroyuki Tomiyama, University of California, Irvine

Nikil Dutt, University of California, Irvine

pp. 97

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Error Diagnosis of Sequential Circuits Using Region-Based Model (Abstract)

Anand L. D'Souza, Sun Microsystems

Michael S. Hsiao, Rutgers University

pp. 103

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Session 2A: Test I

On Improving Static Test Compaction for Sequential Circuits (Abstract)

Ruifeng Guo, University of Iowa

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 111

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On Fault-Simulation Through Embedded Memories On Large Industrial Designs (Abstract)

Sitaram Yadavalli, Intel Corporation

Sandip Kundu, Intel Corporation

pp. 117

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A Novel Strategy to Test Core Based Designs (Abstract)

Debabrata Bagchi, Indian Institute of Technology, Kharagpur

Dipanwita RoyChowdhury, Indian Institute of Technology, Kharagpur

Joy Mukherjee, Indian Institute of Technology, Kharagpur

Shantanu Chattopadhyay, Indian Institute of Technology, Guwahati

pp. 122

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Testable Design of Sequential Circuits with Improved Fault Efficiency (Abstract)

Debesh K. Das, Jadavpur University

Bhargab B. Bhattacharya, Indian Statistical Institute

Satoshi Ohtake, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 128

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Combination of Structural and State Analysis for Partial Scan (Abstract)

Sameer Sharma, Intel Corporation

Michael S. Hsiao, Rutgers University

pp. 134

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Session 2B: Test II

Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model (Abstract)

Yong Chang Kim, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

Vishwani D. Agrawal, Lucent Tech.

pp. 143

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Synthesis of System-on-a-chip for Testability (Abstract)

Srivaths Ravi, Princeton University

Niraj K. Jha, Princeton University

pp. 149

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Timing Verification and Delay Test Generation for Hierarchical Designs (Abstract)

Arun Krishnamachary, The University of Texas at Austin

Jacob A. Abraham, The University of Texas at Austin

Raghuram S. Tupuri, Advanced Micro Devices

pp. 157

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A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification (Abstract)

Jian-Kun Zhao, University of Illinois at Urbana Champaign

Jeffrey A. Newquist, University of Illinois at Urbana Champaign

Janak H. Patel, University of Illinois at Urbana Champaign

pp. 163

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Session 2C: Verification

Implementation of Read- k-times BDDs on Top of Standard BDD Packages (Abstract)

Wolfgang Gunther, Albert-Ludwigs-University

Rolf Drechsler, Siemens AG Corporate Technology

pp. 173

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Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model (Abstract)

Siddharth R. Phanse, Tata Institute of Fundamental Research

R.K Shyamasundar, Tata Institute of Fundamental Research

pp. 179

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Design Verification and Functional Testing of Finite State Machines (Abstract)

Mark W. Weiss, University of Nebraska-Lincoln

Sharad C. Seth, University of Nebraska-Lincoln

Shashank K. Mehta, Pune University

Kent L. Einspahr, Concordia University

pp. 189

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Design Of Provably Correct Storage Arrays (Abstract)

R.V. Joshi, T.J. Watson Research Center

W. Hwang, T.J. Watson Research Center

A. Kuehlmann, T.J. Watson Research Center

pp. 196

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Session 3A: Low-Power I

Low-Power Wireless Sensor Networks (Abstract)

Rex Min, Massachusetts Institute of Technology

Manish Bhardwaj, Massachusetts Institute of Technology

Seong-Hwan Cho, Massachusetts Institute of Technology

Eugene Shih, Massachusetts Institute of Technology

Amit Sinha, Massachusetts Institute of Technology

Alice Wang, Massachusetts Institute of Technology

Anantha Chandrakasan, Massachusetts Institute of Technology

pp. 205

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Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic (Abstract)

Hendrawan Soeleman, Purdue University

Kaushik Roy, Purdue University

Bipul Paul, Purdue University

pp. 211

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Average Power in Digital CMOS Circuits using Least Square Estimation (Abstract)

Ashok K. Murugavel, University of South Florida

N. Ranganathan, University of South Florida

R. Chandramouli, University of South Florida

Srinath Chavali, University of South Florida

pp. 215

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Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces (Abstract)

Amit Sinha, Massachusetts Institute of Technology

Anantha P. Chandrakasan, Massachusetts Institute of Technology

pp. 221

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Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits (Abstract)

Nikhil Tripathi, Indian Institute of Technology, Kharagpur

Amit Bhosle, Indian Institute of Technology, Kharagpur

Debasis Samanta, Indian Institute of Technology, Kharagpur

Ajit Pal, Indian Institute of Technology, Kharagpur

pp. 227

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Session 3B: Low-Power II

Accurate Power Macro-modeling Techniques for Complex RTL Circuits (Abstract)

Nachiketh R. Potlapally, Rutgers University

Michael S. Hsiao, Rutgers University

Anand Raghunathan, NEC USA

Ganesh Lakshminarayana, NEC USA

Srimat T. Chakradhar, NEC USA

pp. 235

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Architecture of Reconfigurable a Low Power Gigabit ATM Switch (Abstract)

Abhijit M. Lele, Indian Institute of Science

S.K. Nandy, Indian Institute of Science

pp. 242

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Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks (Abstract)

David Duarte, The Pennsylvania State University

Vijaykrishnan Narayanan, The Pennsylvania State University

Mary Jane Irwin, The Pennsylvania State University

Mahmut Kandemir, The Pennsylvania State University

pp. 248

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Software Power Optimizations In An Embedded System (Abstract)

Vishal Dalal, Silicon Automation Systems Limited

C.P. Ravikumar, Indian Institute of Technology

pp. 254

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Session 3C: Analog Design

Library Binding for High-Level Synthesis of Analog Systems (Abstract)

Sree Ganesan, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 261

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An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage (Abstract)

Jackson Harvey, University of Minnesota

Ramesh Harjani, University of Minnesota

pp. 269

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A Code Transition Delay Model for ADC Test (Abstract)

Sanjay Mohan, Rutgers University

Michael L. Bushnell, Rutgers University

pp. 274

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Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices (Abstract)

Alper Demir, Bell Laboratories

David Long, Bell Laboratories

Jaijeet Roychowdhury, Bell Laboratories

pp. 283

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Session 4A: FPGA

Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks (Abstract)

pp. 291

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Fpga Hardware Synthesis From Matlab (Abstract)

Malay Haldar, MACH Design Systems, Inc.

Anshuman Nayak, MACH Design Systems, Inc.

Alok Choudhary, MACH Design Systems, Inc.

Prith Banerjee, MACH Design Systems, Inc.

Nagraj Shenoy, Northwestern University

pp. 299

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Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators (Abstract)

N. Shenoy, Northwestern University

P. Banerjee, Northwestern University

A. Choudhary, Northwestern University

M. Kandemir, Northwestern University

pp. 305

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Performance Driven Optimization for MUX based FPGAs (Abstract)

Wolfgang Gunther, Albert-Ludwigs-University

Rolf Drechsler, Siemens AG Corporate Technology

pp. 311

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Application Specific Macro Based Synthesis (Abstract)

Sujatha Sundararaman, University of Cincinnati

Sriram Govindarajan, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 317

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Session 4B: Physical Design I

Modeling of Nonuniform Interconnects by Using Differential Quadrature Method (Abstract)

Qinwei Xu, University of Michigan

Pinaki Mazumder, University of Michigan

Mayukh Bhattacharya, University of Michigan

pp. 327

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A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits (Abstract)

Sujit T. Zachariah, Intel Corporation

Sreejit Chakravarty, Intel Corporation

pp. 333

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How to Half Wire Lengths in the Layout of Cyclic Shifters (Abstract)

Mark A. Hillebrand, University of Saarland

Thomas Schurger, University of Saarland

Peter-Michael Seidel, Southern Methodist University

pp. 339

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Partitioning Routing Area into Zones with Distinct Pins (Abstract)

K. Sinha, Kalyani Engineering College

S. Sur-Kolay, Indian Statistical Institute

B.B. Bhattacharya, Indian Statistical Institute

P.S. Dasgupta, Indian Institute of Management

pp. 345

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Session 4C: Physical Design II

Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies (Abstract)

Sabyasachi Sengupta, Texas Instruments (India) Ltd.

Somavalli Ramanathan, Texas Instruments (India) Ltd.

Biswadeep Chatterjee, Texas Instruments (India) Ltd.

Dibyendu Goswami, Texas Instruments (India) Ltd.

pp. 353

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Transmission Line Modeling by Modified Method of Characteristics (Abstract)

Qinwei Xu, University of Michigan

Pinaki Mazumder, University of Michigan

Zheng-Fan Li, Shanghai Jiao Tong University

pp. 359

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Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations (Abstract)

Nagaraj Ns, Texas Instruments Inc.

Poras Balsara, University of Texas at Dallas

Cyrus Cantrell, University of Texas at Dallas

pp. 365

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Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs (Abstract)

Marcello Lajolo, NEC USA

Matteo Sonza Reorda, Politecnico di Torino

Massimo Violante, Politecnico di Torino

pp. 371

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Session 5A: Built-In Test

An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers (Abstract)

D.C. Huang, National Chung-Cheng University

W.B. Jone, National Chung-Cheng University

S.R. Das, University of Ottawa

pp. 379

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Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits (Abstract)

Dilip Bhavsar, Compaq Computer Corporation

Rishan Tan, Compaq Computer Corporation

pp. 385

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Efficient Signature-Based Fault Diagnosis Using Variable Size Windows (Abstract)

Thomas Clouqueur, University of Wisconsin-Madison

Ozen Ercevik, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

Hiroshi Takahashi, Ehime University

pp. 391

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A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers (Abstract)

D.C. Huang, National Chung-Cheng University

W.B. Jone, National Chung-Cheng University

S.R. Das, University of Ottawa

pp. 397

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Hierarchical Cellular Automata As An On-Chip Test Pattern Generator (Abstract)

Biplab K. Sikdar, Bengal Engineering College (D.U)

Purnabha Majumder, Bengal Engineering College (D.U)

Monalisa Mukherjee, Bengal Engineering College (D.U)

P. Pal Chaudhuri, Bengal Engineering College (D.U)

Debesh K. Das, Jadavpur University

Niloy Ganguly, IISWBM

pp. 403

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Session 5B: Synthesis

High Level Synthesis Of Multi-Precision Data Flow Graphs (Abstract)

Vikas Agrawal, Indian Institute of Science

Anand Pande, Broadcom India Pvt. Ltd.

Mahesh M. Mehendale, Texas Instruments (I)Ltd.

pp. 411

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Multilevel Logic Minimization Using Functional Don't Cares (Abstract)

L. Wang

A.E.A. Almaini

pp. 417

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Complexity Of Minimum-Delay Gate Resizing (Abstract)

Supratik Chakraborty, Indian Institute of Technology

Rajeev Murgai, Fujitsu Laboratories of America, Inc.

pp. 425

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Synthesis Of Transparent Circuits For Hierarchical And System-On-A-Chip Test (Abstract)

Krishnendu Chakrabarty, Duke University

Andrew Exnicios, Duke University

Rajatish Mukherjee, University of Tulsa

pp. 431

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Session 5C: Architecture

Scaling Up Of Wave Pipelines (Abstract)

Masa-aki Fukase, Hirosaki University

Ryusuke Egawa, Hirosaki University

Tomoaki Sato, Tohoku University

Tadao Nakamura, Tohoku University

pp. 439

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Vlsi Architectures For High-Speed Map Decoders (Abstract)

Alexander Worm, University of Kaiserslautern

Holger Lamm, University of Kaiserslautern

Norbert Wehn, University of Kaiserslautern

pp. 446

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Design Of Multiple Attractor Gf (2p) Cellular Automata For Diagnosis Of Vlsi Circuits (Abstract)

Biplab K. Sikdar, Bengal Engineering College (D.U)

Purnabha Majumder, Bengal Engineering College (D.U)

P. Pal Chaudhuri, Bengal Engineering College (D.U)

Niloy Ganguly, IISWBM

pp. 454

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Synthesizing A Long Latency Unit Within Vliw Processor (Abstract)

Ram Lakhan Gupta, Alliance Semiconductor

Anshul Kumar, I. I. T. Delhi

A. Van Der Werf, Philips Research

G. Natalino Busa, Philips Research

pp. 460

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Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance (PDF)

Session 6A: Technology I

J. Bude

pp. 469

Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates (Abstract)

Mayukh Bhattacharya, The University of Michigan

Pinaki Mazumder, The University of Michigan

Ronald J. Lomax, The University of Michigan

pp. 470

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Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering (Abstract)

G. Shrivastav, Indian Institute of Technology

S. Mahapatra, Indian Institute of Technology

V. Ramgopal Rao, Indian Institute of Technology

J. Vasi, Indian Institute of Technology

K.G. Anil, Universitaet der Bundeswehr

C. Fink, Universitaet der Bundeswehr

W. Hansch, Universitaet der Bundeswehr

I. Eisele, Universitaet der Bundeswehr

pp. 475

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Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics (Abstract)

Nihar. R. Mohapatra, Indian Institute of Technology

A. Dutta, Indian Institute of Technology

M.P. Desai, Indian Institute of Technology

V. Ramgopal Rao, Indian Institute of Technology

pp. 479

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Session 6B: Technology II

Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions (Abstract)

R.K. Jarwal, New Jersey Institute of Technology

D. Misra, New Jersey Institute of Technology

pp. 485

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High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors (Abstract)

B. Prasad, Kurukshetra University

P.J. George, Kurukshetra University

Chandra Shekhar, CEERI

pp. 491

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An On-Chip Coupling Capacitance Measurement Technique (Abstract)

Pratheep A. Nair, Indian Institute of Technology

Anubhav Gupta, Indian Institute of Technology

Madhav P. Desai, Indian Institute of Technology

pp. 495

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Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports (Abstract)

Shabbir H. Batterywala, Silicon Automation Systems Ltd.

H. Narayanan, Indian Institute of Technology

pp. 500

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Session 6C: Deep Sub-Micron

Repeater Insertion To Minimise Delay In Coupled Interconnects (Abstract)

Dinesh Pamunuwa, Royal Institute of Technology

Hannu Tenhunen, Royal Institute of Technology

pp. 513

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Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs (Abstract)

Arvind N V, Texas Instruments India Ltd.

Suresh P R, Texas Instruments India Ltd.

Sivakumar V, Texas Instruments India Ltd.

Chandrani Pal, Texas Instruments India Ltd.

Debaprasad Das, Texas Instruments India Ltd.

pp. 518

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Switching Noise Analysis Framework For High Speed Logic Families (Abstract)

M. Delaurenti, Politecnico di Torino

M. Graziano, Politecnico di Torino

G. Masera, Politecnico di Torino

G. Piccinini, Politecnico di Torino

M. Zamboni, Politecnico di Torino

pp. 524

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Estimating Crosstalk From Vlsi Layouts (Abstract)

V. Sankara Subramanian, ATI Research Silicon Valley Inc

C.P. Ravikumar, Indian Institute of Technology

pp. 531

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Author Index (PDF)

pp. 537

VLSI Design 2002 Call for Papers (PDF)

pp. 540

5th IEEE VLSI Design and Test Workshops 2001 Call for Participation (PDF)

pp. 541